Tech jobs

North AmericaContractStaff H-1B sponsor history

Staff Electrical Engineer - Sensor FPGA and PCB (Aggregator)

ai assembly ethernet fpga image-processing +8 skills

Staff Electrical Engineer for Apollo’s sensor bridge, focusing on FPGA hardware (PCBA design, RTL development) and high-speed/mixed-signal electronics. Core technologies include FPGA (VHDL/Verilog), high-speed interfaces (CSI-2, GMSL2, 10GbE), and sensor aggregation.

Ayo Semiconductor

Open 49d On-siteNorth AmericaFull-timePrincipal

Principal FPGA Engineer

ai asic cpp embedded-systems fpga +3 skills

Principal FPGA Engineer at a photonic AI compute startup, writing and deploying RTL (Verilog/VHDL) and embedded C/C++ to FPGAs for chip verification and prototype development, fully onsite in Boston.

Ayo Semiconductor

Open 59d On-siteNorth AmericaFull-timeSenior

Senior FPGA Engineer

ai asic cpp embedded-systems fpga +3 skills

Senior FPGA Engineer writing and deploying RTL (Verilog/VHDL) and embedded C/C++ to FPGAs for chip verification and prototype development of photonic AI processors.

neuralink

Open 81d North AmericaFull-time H-1B sponsor history

Hardware/ Software Co-Design Engineer

ai cpp embedded-software firmware machine-learning +5 skills

Designs low-power digital processors and hardware accelerators for brain-computer interfaces, implementing RTL and collaborating with firmware teams using SystemVerilog, C/C++, and Python.

151 000 – 261 000 $

neuralink

Open 81d North AmericaFull-time H-1B sponsor history

Digital IC Design Engineer

ai cpp firmware machine-learning python +3 skills

Designs low-power digital processors and hardware accelerators for brain-computer interfaces using SystemVerilog, C/C++, and Python.

116 000 – 233 800 $

Anduril Industries

Open 81d North AmericaFull-timeSenior H-1B sponsor history

Senior FPGA Engineer, Space

ai computer-vision cpp ethernet firmware +7 skills

Design and implement FPGA/SoC firmware for space-domain systems using Xilinx tools and VHDL/Verilog, integrating third-party IP and ensuring space-grade performance.

191 000 – 253 000 $

Anduril Industries

Open 32d North AmericaContractSenior H-1B sponsor history

Senior Electrical Test Engineer, Intelligence Systems

ai altium analytics automation computer-vision +13 skills

Designs and builds complex test systems and PCBs to validate defense electronics, integrating FPGAs, MCUs, and data-acquisition gear for high-reliability military hardware.

146 000 – 194 000 $

Anduril Industries

North AmericaFull-time H-1B sponsor history

Digital Design Engineer, Air Dominance and Strike

ai asic ci-cd computer-vision embedded-software +18 skills

Digital Design Engineer at Anduril Industries developing FPGA and SoC platforms for high-performance embedded systems, avionics, and mission-critical hardware using RTL design in VHDL/Verilog/SystemVerilog.

146 000 – 194 000 $

Advanced Micro Devices, Inc

ai cad perl python rtl +1 skills

Physical Design Power Methodology Senior Staff Engineer

North AmericaStaff

Define and optimize power methodologies for AMD’s next-gen CPU/GPU/SOC designs, driving performance/watt from synthesis to route using tools like PrimePower and scripting in Perl/Tcl/Python.

SambaNova Systems

North AmericaContractSenior H-1B sponsor history

Senior Technical Recruiter - Hardware

ai asic cloud generative-ai github +1 skills

Senior Technical Recruiter owning full-lifecycle hardware recruiting (Design Verification, ASIC, physical design, PCB/systems) at an AI chip company, using Greenhouse ATS and sourcing via LinkedIn and GitHub.

170 000 – 230 000 $

Renesas Electronics

Staff/ Sr Staff Engineer, Digital Design

APACFull-timeSenior

agile ai asic bash perl +4 skills

The Staff/Sr Staff Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within Renesas MCU products. The role involves collaborating with cross-functional teams to ensure PPA targets are met using industry-standard EDA tools.

Renesas Electronics

Principal Engineer, Digital Design

APACFull-timeSenior

agile ai asic bash perl +4 skills

The Principal Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within MCU SoCs. The role involves collaborating with cross-functional teams to ensure PPA targets are met while mentoring junior engineers and improving design methodologies.

Advanced Micro Devices, Inc

Senior Lead Verification Engineer

Open 75d APACLead

ai asic embedded-systems perl rtl +3 skills

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…

Syntiant

APACStaff H-1B sponsor history

Senior Staff Digital Design Engineer - Audio DSP Algorithm

ai asic cpp deep-learning matlab +7 skills

The Senior Staff Digital Design Engineer will lead the design, implementation, and verification of DSP algorithms and digital control logic for audio processing within ASIC systems. This role involves the full ASIC design flow, from specification to silicon bring-up, utilizing expertise in digital signal processing and mixed-signal integrated circuits.

Open 75d North AmericaPrincipal

Principal ASIC Design Engineer

asic cloud networking perl python +2 skills

Designs and develops complex ASIC modules for high-performance networking chips, focusing on architecture, RTL implementation, verification, and power/performance optimization. Leads cross-functional teams and mentors junior engineers.

174 000 – 352 500 $

Open 75d North AmericaSenior

Senior Physical Design Engineer

bash cloud linux perl python +3 skills

Designs and implements large SoC physical layouts from RTL to GDSII, including floorplanning, place & route, power grids, and sign-off verification for high-performance chips.

174 000 – 352 500 $

ASIC Design Engineer

Open 75d North America

agentic-ai ai asic cloud networking +4 skills

The ASIC Design Engineer will develop high-speed networking chips from specification to netlist, working on micro-architecture, RTL implementation, and timing closure. The role involves collaborating with verification and physical design teams to ensure high-performance silicon for networking hardware.

120 000 – 243 000 $

Open 75d North AmericaSenior

Sr. ASIC Design Engineer

agentic-ai ai asic cloud networking +4 skills

Design high-speed networking ASICs from spec to netlist using Verilog/SystemVerilog, work with physical design for timing closure, and collaborate with verification teams.

153 500 – 310 500 $

Open 75d North AmericaPrincipal

Principal Physical Design Engineer