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FPGA Engineer
Design FPGA/ASIC solutions for ultra-low-latency trading systems, from architecture to live hardware bring-up, using SystemVerilog/Verilog and vendor tools.
Sr. FPGA Design & Verification Engineer
Design and verify FPGA-based hardware for Dolby’s cinema servers, audio processors, and HDR projection systems using VHDL/Verilog/SystemVerilog and advanced verification tools.
Senior ASIC Design Verification Engineer, Google Cloud
Design and verify custom TPU silicon for Google’s AI workloads using SystemVerilog/UVM, driving full verification cycles from planning to tape-out.
Staff SerDes DSP RTL Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Senior FPGA Engineer - Systems Team
Senior FPGA engineer designs and deploys low-latency quantum control systems, integrating FPGA hardware with customer setups and troubleshooting quantum experiments.
SOC Emulation Engineer - Hardware Emulation Infrastructure
Develops and maintains hardware emulation infrastructure for chip design teams, integrating transactors and writing Python/C++ test frameworks to validate silicon before tape-out.
Senior Staff Digital Design Engineer
Lead digital design for advanced RAIN RFID reader chips, owning RTL through tapeout and silicon validation while mentoring engineers and improving ASIC flows.
Staff Design Verification Engineer, AI HW
Design Verification Engineer builds and runs tests for AI-native compute cores and RISC-V CPUs using SystemVerilog, Python, and CI pipelines to ensure hardware correctness before tape-out.
Staff Design Verification Engineer - Edinburgh/Cambridge
Design verification engineer at AMD, building and automating testbenches to verify next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.
Senior Engineer - ASIC Design
Design ASIC IP blocks and subsystems for 5G/6G mobile networks using SystemVerilog, AMBA protocols, and RTL sign-off tools.
Staff Silicon Design Verification Engineer (PCIe)
Verify next-gen PCIe controller subsystems for AMD’s SoCs, using UVM, SystemVerilog, and low-power flows to ensure performance and power targets for AI, gaming, and server chips.
ASIC Design Engineer
Design and develop DSP blocks for quantum computing systems using ASIC flows, RTL, and EDA tools while collaborating with cross-functional teams.
Digital ASIC Designer (EP-ESE-ME-2026-134-GRAP)
Design a radiation-tolerant RISC-V microcontroller ASIC for CERN’s particle physics detectors using 65/28 nm CMOS, RTL-to-tapeout with fault-tolerant techniques and post-silicon validation.
FPGA Engineer
Design and optimize FPGA/SoC solutions for high-performance digital signal processing and RF applications using Xilinx devices and Vivado.
Senior FPGA Prototyping Engineer
Own FPGA prototyping, firmware enablement, and first-silicon bring-up for next-gen satellite communications ASICs, bridging ASIC design, firmware, and system integration.
Senior FPGA Prototyping Engineer
Own FPGA prototyping, firmware enablement, and first-silicon bring-up for next-gen satellite communications ASICs, using Verilog, Xilinx tools, and high-speed interfaces.
Senior FPGA Engineer
Design and verify FPGA firmware for spacecraft subsystems using VHDL/SystemVerilog, ensuring real-time control and fault tolerance for high-power satellite missions.
FPGA Designer
Design and deliver FPGA-based systems using Xilinx/Intel tools, RTL/Verilog/VHDL, and collaborate across teams to close timing and debug prototypes for clients in high-speed electronics.
Microarchitect / RTL Design - Network Datapath & MAC Engine
Design high-performance Ethernet MAC engines and network datapaths for AI-driven ASICs, ensuring line-rate performance and protocol compliance using SystemVerilog and AI-assisted flows.
Principal Firmware Engineer
Principal firmware engineer leading FPGA development for aerospace navigation systems, defining standards and mentoring teams to ensure DO-254 compliance and high-reliability designs.