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Silicon Design Engineer
The SMTS Silicon Design Engineer will develop host controller IP for high-speed I/O technologies using Verilog HDL. This role involves designing, verifying, and mentoring junior engineers to support next-generation high-performance computing and AI products.
IP Verification Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Senior SoC Design Verification Engineer
The Senior SoC Design Verification Engineer leads the verification of complex SoC features and subsystems using SystemVerilog and UVM. The role involves driving verification methodology, ensuring silicon sign-off, and mentoring engineering teams.
DFX RTL Design Engineer
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
Program Manager (Chip Development)
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
Senior ADC Design Engineer
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
Senior PLL Design Engineer
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
Senior Analog / Mixed-Signal IC Design Engineer
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
ASIC Engineering Program Manager
Lead multi-functional ASIC and hardware platform programs from concept to production, coordinating silicon, firmware, and system teams to deliver Cisco’s next-gen networking solutions.
Talent Acquisition Specialist
About the role Great teams aren’t hired by accident. The best engineers on this team didn’t apply — someone found them, wrote them a message worth answering, and ran a process so clean they never drifted toward another…
Campus FPGA Engineer (Intern)
An intern designs ultra-low-latency FPGA systems for trading infrastructure, working with hardware design, RTL, and performance optimization alongside a small engineering team.
2027 Internship- Hardware Engineer (FPGA)
Intern designs FPGA/ASIC hardware for ultra-low latency trading systems, coding in SystemVerilog/Python and bringing designs to life on real silicon.
Embedded Firmware Engineer
Develop and verify embedded firmware in C/C++ for mixed-signal power management ICs, collaborating with RTL teams to define hardware interfaces and ensure ROM-ready code.
RTL Design Engineer
Design and integrate RTL for mixed-signal power management IP, drive timing closure, and tape-out while collaborating with analog, firmware, and physical design teams.
ASIC Design Verification Engineer
ASIC Design Verification Engineer responsible for owning verification strategy, coverage closure, and system-level testing for AMD’s mixed-signal power management IP, including RTL design and collaboration with analog/firmware teams.
Staff Silicon Design Engineer
Leads verification of complex SoC subsystems (e.g., memory/cache, coherency, PCIe/DDR) using UVM/SystemVerilog, ensuring functionality, performance, and security. Owns test strategy, debugging, and cross-team collaboration for sign-off.
Silicon Design Engineer - Core Debug
Core Debug Engineer at AMD verifies next-gen microprocessor designs, collaborates with RTL engineers, and resolves complex logic bugs to ensure functionality and architectural compliance.