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Member of Technical Staff (MTS) – Firmware Engineer
Design and maintain embedded firmware for high-speed networking and semiconductor products, including drivers, HAL, and validation tools using C/C++ and hardware interfaces.
Physical Design Engineer (Advanced Node / ASIC / Full Flow Implementation)
Physical design engineer implementing advanced ASICs from netlist to GDSII using PnR tools, focusing on timing closure, PPA optimization, and tape-out signoff.
Mixed Signal Logic Design Engineer
Job Details: Job Description: The Role and Impact As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of industry-leading technologies by contributing to the development of…
Senior Engineer, Design Automation Methodologies
Designs and automates ASIC front-end methodologies for IP/SoC projects, using EDA tools like SpyGlass and scripting in Python/Perl/TCL to improve design checks and integration flows.
Lead Design Verification Engineer
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Graduate Talent FPGA IP Software Development
Graduate trainee develops FPGA IP cores using HDL, RTL design, and verification, working with tools like Vivado/Quartus and collaborating on real-world FPGA-based system projects.
FPGA Silicon Validation Engineer
Validate high-speed I/O and PHY designs for FPGA silicon, including DDR/LPDDR and MIPI interfaces, using lab tools and automation.
FPGA Silicon Design Verification Engineer
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
FPGA Silicon Design Verification Engineer
Design Verification Engineer builds UVM testbenches and runs pre-silicon verification for FPGA DFT logic like scan, MBIST, and JTAG to ensure silicon quality before tape-out.
DFT Digital Design Engineer (f/m/d)
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows to improve SoC test coverage and silicon yield while collaborating with cross-functional teams.
Physical Design STA Engineer
Design and optimize physical design, STA, and power integrity flows for high-speed networking chips and SoCs using tools like PrimeTime and PrimePower.
Physical Design Engineer
Designs and optimizes semiconductor physical layouts for FPGAs, guiding RTL through GDSII with timing, power, and verification signoff.
Sr FPGA Designer
Design and implement FPGA logic in System Verilog for surgical robotics, focusing on video processing, motor control, and high-speed comms, then verify and integrate the designs into complete medical systems.
Mask Layout Designer
Designs and verifies advanced SRAM and analog/mixed-signal mask layouts for AMD’s processors, ensuring DRC/LVS compliance and collaborating with global teams to meet tape-out schedules.
PLL Design Engineer
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Physical Design Engineer
You drive physical implementation and sign-off of critical blocks for AI and high-performance computing silicon. You own designs from RTL to GDSII, optimize floorplans, placement, clocking, routing, timing, power, and…
PLM Software Developer
Develop and customize PLM software integrations with Siemens Teamcenter and Windchill, collaborating with cross-functional teams to translate requirements into technical solutions.
Principal Digital Design Engineer
Principal engineer leads a small team designing high-performance FPGA/ASIC Front Haul Gateway solutions for cellular infrastructure radios, using Verilog, SystemVerilog, and AMD Vivado tooling.