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Senior Physical Design Engineer - Contract
Senior Physical Design Engineer Overview: As a Physical Design Engineer, you will be a key contributor to the development of their cutting-edge multi-core in-memory compute SoCs. This role involves hands-on…
DevOps Engineer - Electronics
DevOps Engineer - Electronics background required - Fully remote role - £460 per day inside IR35 My client, a leading AI business is seeking a fully remote DevOps Engineer with a background in electronics to to offer…
Senior ASIC Design Engineer — Data Center Networking
Senior ASIC Design Engineer at AMD designing complex ASIC blocks for high-performance networking silicon, working across verification, physical design, and validation to achieve first-silicon success.
Principal Physical Design Engineer
Leads the physical design and tape-out of advanced AI and data-center SoCs, using EDA tools to optimize performance, power, and manufacturability.
Full Stack Engineer
Own features end-to-end using React, Vue, or Angular with TypeScript and backend services like Node.js, Python, Java, Go, or C# on Azure. You will handle Oracle database design, cloud-native deployment, and support AI workloads on NVIDIA GPU infrastructure.
UIUC Research Park Intern - FPGA Design
About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we…
Low Power Design Engineer (RTL)
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Hardware Engineer, Architect
Design custom silicon and system microarchitecture for an unconventional AI compute platform, translating transformer and diffusion workloads into energy-efficient mixed-signal compute tiles and memory hierarchies.
Senior Digital Hardware Engineer (RTL & Verification) Zurich | Hybrid
Design and verify digital IP blocks (SystemVerilog RTL) for next-gen compute chips, using UVM testbenches and collaborating with analog/custom teams.
Digital ASIC Design Engineer
Designs and optimizes digital ASICs for next-gen semiconductor systems, handling RTL coding, synthesis, timing analysis, and validation in a high-tech Swiss engineering environment.
Lead ASIC Physical Design Engineer – Advanced Nodes
Lead a team to architect and implement advanced ASIC physical design flows from RTL to GDSII, optimizing timing, power, and reliability for next-gen compute chips.
HWIL FPGA Engineer
Design and implement FPGA-based real-time Hardware-in-the-Loop systems for defense-grade hardware validation, integrating high-fidelity simulations with physical sensors and avionics.
Data Accelerator - RTL Design Engineer – Lead
Lead a team designing custom hardware accelerators for servers and data centers using RTL, ASIC flows, and scripting tools.
Senior Principal FPGA & Digital Signals Processing Engineer
Lead FPGA firmware architecture for a portable SIGINT/EW platform, migrating GPU DSP algorithms to FPGA and optimizing real-time RF signal processing for defense missions.
Lead ReactJS Developer
Lead a team to architect and build large-scale React.js applications with TypeScript, Redux Toolkit, and React Router, while mentoring developers and optimizing performance.