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Staff Silicon Design Engineer
Build and deploy AI agents that automate silicon IP design workflows using RAG, structured tool execution, and EDA tool integration to accelerate spec-to-netlist cycles.
Senior FPGA Engineer (TS/SCI)
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
Senior Design Engineer
About ChipAgents ChipAgents is revolutionizing chip design and verification with agentic-AI workflows. Founded by experts in AI and semiconductor design, we partner with top-10 semiconductor companies, hyperscale cloud…
Principal Digital Design Engineer
Principal engineer leads a small team designing high-performance FPGA/ASIC Front Haul Gateway solutions for cellular infrastructure radios, using Verilog, SystemVerilog, and AMD Vivado tooling.
Frontend Developer React / TypeScript / IA
Build modern React/TypeScript frontends with Azure cloud integration, focusing on greenfield projects and real-time data. Work with AI/LLM APIs and ensure WCAG 2.1 AA accessibility.
Data Engineer F/H H/F
Build and maintain robust data pipelines on AWS to process terabytes of media audience, adserver, and CRM data, enabling predictive products and ad-revenue insights.
Développeur Full Stack (H/F) | Aix-en-Provence
Build and optimize scalable SaaS and on-premise software using Node.js, React, PostgreSQL, Docker and Kubernetes in an agile, DevOps-driven team.
Développeur Full Stack Java / Groovy et Angular H/F
Build and maintain full-stack Java/Groovy and Angular applications for M6 Group’s media platforms, including radio tools, public sites, and internal systems using Spring Boot, microservices, and Angular 18.
Software Engineer (f/m/d) – Data Platforms
Build and scale data pipelines for TV and advertising analytics using Spark, Scala, and AWS; own resilient, cloud-native platforms handling terabytes daily.
Hardware Engineer, RTL
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across architecture, verification, and physical design to tape out custom ASICs.
Senior Engineering Program Manager
Own the end-to-end SoC program for a next-gen Physical AI chip, coordinating silicon, platform, software, and vendor teams from architecture through tapeout and bring-up.
Distinguished Technologist, ASIC Design Architect
Architect high-performance ASICs for networking hardware, defining microarchitecture, RTL design, and silicon bring-up while balancing performance, power, and schedule constraints.
Campus FPGA Engineer (Intern)
Designs ultra-low-latency FPGA-based systems for real-time trading acceleration using RTL and hardware design, working alongside experts in a research-driven finance firm.
ASIC RTL Design Engineer
Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Senior Staff Design Verification Engineer
Design Verification Engineer at Cerebras, building and testing the world's largest AI chip to ensure first-silicon success and ultra-fast AI inference.
Lead RTL Design Engineer
Lead the design of Cerebras' next-generation AI chips, focusing on high-performance RTL development and integration while collaborating with cross-functional teams and external ASIC vendors.