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Fellow Architect, Functional & Performance Verification
Lead AMD’s pre-silicon verification strategy, defining next-gen architectures and methodologies to ensure first-pass silicon success for complex SoC designs using advanced EDA tools and ML/AI innovations.
ASIC Design Engineer
Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the…
FPGA Engineering Intern - Summer 2027
Build FPGA-based ultra-low-latency trading systems in Verilog/VHDL, automate RTL generation, and collaborate on real-time capital-markets infrastructure.
Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)
Designs and verifies high-speed interface IP for next-gen storage subsystems (NVMe/Chiplet) in ASICs, leading RTL development through silicon bring-up for enterprise and AI data center storage solutions.
Digital Design Verification Engineer
Build and maintain UVM/SystemVerilog testbenches to verify PCIe and memory-subsystem RTL, collaborating with architects and post-silicon teams to ensure robust, high-performance designs.
AI/ML Silicon Verification Solutions Engineer – Tools
Build AI-powered tools to automate and enhance semiconductor verification workflows, using Python, LLMs, and cloud DevOps for faster, smarter hardware development.
IC Design Exploration Intern
An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.
Hardware Engineer, Physical Design
Hardware Engineer specializing in RTL/PD, optimizing designs from microarchitecture to tapeout for AI-native ASICs at Normal Computing, a deep-tech semiconductor startup.
ASIC Design Engineer
Designs and implements ASIC/SoC RTL (Verilog/SystemVerilog) for high-performance SSD controllers, collaborating with verification, validation, and firmware teams to deliver next-gen enterprise and AI data center storage solutions.
Sr. FPGA Engineer II
Designs, codes, and tests FPGA logic for space-based electro-optical systems supporting U.S. defense and intelligence missions using Xilinx tools.
Principal FPGA Engineer
Design and implement FPGA firmware for advanced electro-optical spacecraft payloads supporting U.S. defense and space missions using VHDL and embedded systems.
Principal Design Validation & Test (DVT) Engineer
Principal Engineer leading post-silicon validation and testing of next-gen coherent DSP ASICs for AI and optical networking, ensuring first-silicon readiness and production deployment.
Silicon Design Engineer
Designs and implements advanced semiconductor testchips from RTL to GDSII tapeout, focusing on physical design, timing closure, and silicon validation for high-performance ASIC/FPGA solutions.
CPU Core Design Verification Engineer
Design verification engineer at AMD, building and running tests to validate next-generation x86 CPU cores using C++, Verilog, and SystemVerilog.
Applied AI Engineer, Top Hardware Priorities
Build AI tools that speed up AMD’s hardware and software engineering workflows, such as design optimization, verification, and debugging, by turning manual processes into AI-assisted systems.
Staff CAD And Methodology Design Engineer
Designs and optimizes RTL-to-GDS semiconductor design flows for AMD’s embedded computing projects, maintaining synthesis, place-and-route, and physical signoff tools and methodologies.