Tech jobs

Open 76d APACStaff H-1B sponsor history

Staff/Senior Staff Physical Design Floorplan & PDN Lead

ai cloud design-thinking perl python +2 skills

Leads chip-level floorplanning and power delivery network design for advanced AI hardware SoCs, balancing performance, power, and area while ensuring robust physical integrity.

Open 76d APACPrincipal H-1B sponsor history

Principal Physical Design Engineer (RTL-to-GDSII)

ai cloud data-mining python react +2 skills

Principal Physical Design Engineer at EnCharge AI in Bangalore builds and optimizes RTL-to-GDSII flows for sub-5nm AI hardware using Cadence tools, scripting, and deep PDK expertise.

Open 76d APACSenior H-1B sponsor history

Senior Physical Design Engineer

ai automation cloud python rtl +1 skills

Senior Physical Design Engineer at EnCharge AI in Bangalore optimizes AI hardware blocks from RTL to GDSII using Cadence tools, Tcl/Python automation, and PPA tuning for tape-outs.

Open 76d RemoteAPACStaff H-1B sponsor history

Staff/Senior Staff Physical Design Engineer (Technical Lead)

ai automation cloud data-mining python +3 skills

Leads a small team to design and deliver high-performance AI hardware blocks, optimizing power, performance, and area while managing tape-out milestones using Cadence tools and advanced scripting.

CB Smart Recruit

Open 33d On-siteNorth AmericaFull-timeSenior

Senior Director, Physical Design & Backend Engineering (HPC)

ai automation hpc networking program-management +1 skills

Lead a global team to deliver advanced-node High-Performance Computing (HPC) and AI SoCs from RTL through GDSII and tape-out, optimizing Power, Performance, and Area (PPA) while scaling backend engineering processes.

260 000 – 290 000 $

Advanced Micro Devices, Inc

Design Verification Engineer

Open 33d North America

ai asic cloud cpp firmware +7 skills

Design Verification Engineer at AMD responsible for developing and maintaining tests to verify complex processor architectures and ASIC/SOC designs using Verilog, SystemVerilog, and UVM.

Optiver

FPGA Engineer

Open 76d North America

cpp rtl systemverilog verilog vhdl

Designs and implements high-speed FPGA-based trading systems to accelerate network infrastructure and trading components, working closely with traders and software engineers.

200 000 – 200 000 $

Optiver

cpp rtl systemverilog verilog vhdl

FPGA Engineer

Open 76d Europe

Netherlands

Designs and implements low-latency hardware trading systems using FPGAs and ASICs, collaborating with traders and software engineers to solve complex financial market problems.

Open 79d UK Licensed UK sponsor

Director, Silicon Logical Design

ai automation program-management python rtl +3 skills

Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.

Open 79d UKSenior Licensed UK sponsor

Senior SoC Architect

ai ethernet machine-learning pcie rtl +1 skills

Designs and integrates high-performance AI accelerator SoCs, collaborating with hardware, software, and verification teams to deliver cutting-edge silicon for AI compute.

Open 79d UK Licensed UK sponsor

Silicon Physical Design Engineer

ai api ethernet pcie python +2 skills

Designs and optimizes the physical layout of AI chips using advanced EDA tools and flows, ensuring high-performance and power-efficient designs for next-gen AI superchips.

Open 79d UKStaff Licensed UK sponsor

Staff SoC Architect

ai cpp ethernet machine-learning pcie +4 skills

Designs and integrates high-performance AI accelerator SoCs, collaborating with hardware/software teams to define sub-systems and interfaces for next-gen AI compute platforms.

Open 53d UKPrincipal Licensed UK sponsor

Staff/Principal Logical Design Engineer

ai python rtl systemverilog tcl +1 skills

Designs and implements micro-architecture and RTL for AI chips, collaborating with cross-functional teams to deliver high-quality silicon solutions using SystemVerilog/VHDL and EDA tools.

Open 48d UK Licensed UK sponsor

SoC Architect

Designs and integrates complex System-on-Chip (SoC) architectures for next-gen AI acceleration platforms, working across hardware, software, and system teams to define critical subsystems.

ai ethernet pcie rtl

Open 45d APACStaff Licensed UK sponsor

Staff Silicon Logical Design Engineer - Bengaluru, Multiple Vacancies

ai automation python rtl systemverilog +1 skills

Designs and integrates advanced semiconductor logic for AI chips in Bengaluru, using SystemVerilog, Python, and digital design flows to deliver RTL and microarchitecture for Graphcore’s silicon.

Open 35d APACSenior Licensed UK sponsor

Senior Physical Design Engineer - Bengaluru, Multiple Vacancies

ai api ethernet pcie python +2 skills

Designs and optimizes the physical layout of advanced AI semiconductors using EDA tools, ensuring high-performance, power-efficient chips at leading-edge process nodes.

Black Semiconductor

Open 35d On-siteEuropeFull-timeSenior

Senior Platform & Hardware Applications Engineer (f/m/d)

Germany

Senior engineer who helps customers integrate next-gen graphene-based photonic interconnect chips into high-performance systems, debugs high-speed links, and builds FPGA/ASIC reference designs.

asic cad embedded-software ethernet fiber +7 skills

Anodize

Open 56d North AmericaLead

Lead SoC Design Engineer

asic cad rtl systemverilog verilog

Lead the design of a next-generation edge SoC for a stealth startup, defining microarchitecture, driving PPA tradeoffs, and integrating high-performance IP to power a custom computing platform.

Cisco