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RTL Micro Architect Lead
Leads microarchitecture design for GPU, DSP, and AI/ML accelerators in complex SoCs, defining RTL specs and optimizing performance, power, and area.
(Sr.) ISP RTL Design Manager
Leads a team to design and implement image signal processing (ISP) hardware using Verilog/SystemVerilog/SystemC, optimizing for power and gate count while collaborating with algorithm and system teams.
ISP RTL Design Engineer
Designs and verifies RTL implementations of image signal processing algorithms using Verilog/SystemVerilog/SystemC to optimize for power and gate count.
(Sr./Staff) ISP RTL Design Engineer
Design and implement image signal processing (ISP) algorithms into hardware using Verilog/SystemVerilog/SystemC, optimizing for power and gate count while verifying logic at ISP and system levels.
(Sr./Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them through simulation, and programs embedded C/assembly to meet power, timing, and area targets.
(Sr./Staff) ASIC Design Engineer
Designs and verifies RTL in Verilog/SystemVerilog for on-chip test and diagnostic IP, integrates it into SoCs, and collaborates with analog/mixed-signal teams to detect failures.
(Staff/Sr. Staff) SoC Design Engineer
Designs and implements video-processing and neural-processing SoC architectures in Verilog/SystemVerilog, verifies them, and programs embedded C/assembly to meet power, timing, and area targets.
Firmware Software Engineer
Design and build firmware and tooling to accelerate semiconductor development, working with hardware teams on EDA, verification, and post-silicon validation using C, C++, and Python.
FPGA Engineer II (ONSITE)
Design and verify FPGA/ASIC digital circuits for aerospace/defense avionics, writing RTL in VHDL/Verilog and ensuring DO-254 compliance.
Principal Firmware Engineer
Principal firmware engineer leading FPGA development for aerospace navigation systems, defining standards and mentoring teams to ensure DO-254 compliance and high-reliability designs.
Senior Design Verification Engineer - Interconnect IP
Verify GPU memory subsystem and interconnect IP designs using SystemVerilog/UVM, testplans, and coverage-driven flows to ensure correctness and performance.
Senior/ IC Design Engineer (Physical Design)
Designs and implements ASIC physical design flows (RTL-to-GDS) using AI-assisted EDA tools, focusing on synthesis, timing closure, and tape-out verification.
Digital and Mixed Signal IC Design/DV Engineer
Design and verify mixed-signal ICs for current sensing, using RTL, SystemVerilog, VHDL, and UVM to ensure first-pass silicon success.
Mixed Signal Design Verification (MSDV) Engineer
Designs and verifies mixed-signal ICs, leading pre-tapeout simulations and regressions to ensure silicon meets specs and is manufacturable.
Lead CPU Design Verification Engineer
Lead the verification of next-gen x86 CPU cores, architecting testbenches and coverage plans for high-performance, low-power processor features in a global team.
Staff DFx Methodology Architect
Architect and implement DFx (Design for Test, Debug, etc.) methodologies and RTL for AMD’s AI-focused SoCs and ASICs, ensuring power, performance, and timing targets while collaborating across global teams.
Staff Electrical and Electronic Design Engineer - Future Forward
The Future Forward group within Intuitive Surgical is searching for a Staff Electrical and Electronic Design Engineer to architect, design, and bring up the electronic hardware behind next-generation robotic and vision…
Principal Silicon Design Verification Manager
Leads a silicon engineering team to design and verify complex security-focused subsystems for Windows client products, blending hands-on verification (SystemVerilog/UVM, Python) with team mentorship and AI-driven workflow improvements.