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Hardware - Senior SoC Design Engineer
Designs AI-native SoC architectures and RTL for high-performance, energy-efficient AI compute hardware, collaborating with verification, physical implementation, and silicon bring-up teams to ensure optimal performance and manufacturability.
Hardware - AI Chip Architect
Designs AI-native hardware architectures and RTL implementations for high-performance, energy-efficient AI chips, focusing on chip modules, simulation, and optimization for power, timing, and area.
Senior UI/UX & Graphic Designer
Senior UI/UX & Visual Designer leading product design workflows in Figma, creating brand collateral and presentations, and ensuring Arabic/RTL localization for digital platforms—onsite in Riyadh.
Principal Engineer, SoC Emulation - Hardware Emulation Infrastructure
Develops and maintains hardware emulation infrastructure for chip design teams, integrating transactors and writing Python/C++ test frameworks to validate silicon before tape-out.
Senior Hardware Design Engineer
Design and verify custom digital hardware (RTL in Verilog/SystemVerilog) for AI/ML tensor computation units, spanning architecture through physical implementation support.
Low Latency FPGA Developer
The FPGA Developer will design, implement, and test high-performance RTL for low-latency high-frequency trading strategies. The role requires expertise in VHDL/Verilog, FPGA debugging tools, and collaboration with software teams to optimize trading system performance.
Mid Level ASIC Design Engineer
Design and implement a high-performance, low-power ASIC accelerator for AI inference in autonomous-driving perception modules using Verilog, SoC IP integration, and timing/power optimization.
Senior FPGA Design Engineer
Designs and optimizes ultra-low-latency FPGA hardware for electronic trading systems used by top-tier financial institutions.
FPGA Design Engineer II
FPGA Design Engineer responsible for RTL design, development, and optimization of high-performance, ultra-low latency FPGA compute and networking systems for electronic trading infrastructure, primarily using SystemVerilog/VHDL.
Hardware Engineer
Designs and develops high-speed, high-density trading hardware (PCBs, custom silicon, antennas) for financial markets, from schematic capture to production, while collaborating with multidisciplinary teams to optimize performance and latency.
Senior Frontend Platform Engineer
Build and maintain Parloa’s frontend platform—microfrontends, design system, and Server-Driven UI—using TypeScript, React, and modern tooling to ship enterprise AI agent management UIs at speed.
Performance Architect, AI HW
Designs and optimizes AI hardware performance by modeling workloads, analyzing bottlenecks, and guiding architectural decisions for next-gen AI systems using C++ and Python.
Mixed-Signal IC Design Engineer
Design and deliver high-performance digital subsystems within mixed-signal ICs, owning the full flow from RTL design through synthesis, P&R, and tape-out using Verilog/SystemVerilog and industry EDA toolchains.