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Senior FPGA Engineer - Chesterton
Design and build real-time FPGA-based hardware systems using SystemVerilog/VHDL, PCIe, and Ethernet in a fast-growing Cambridge startup.
FPGA Emulation Engineer
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
FPGA Engineer
Design and implement FPGA blocks for high-rate data transport and signal processing in satellite ground stations, using Verilog/SystemVerilog and Python.
FPGA Engineer
Design and implement FPGA-based networking and DSP blocks for satellite ground stations, ensuring resilient, high-rate data links for real-time space communications.
Power Management Design Engineer
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
SoC Verification Architect / SoC TB Architect
Leads verification architecture for complex SoCs using SystemVerilog/UVM, driving tape-out readiness for advanced compute subsystems like GPUs and AI accelerators.
RTL Design
Design and implement RTL for next-gen ASICs using Verilog/SystemVerilog, optimizing for performance, power, and area while collaborating with cross-functional teams.
RTL Micro Architect Lead
Lead RTL design and microarchitecture for high-performance SoC subsystems like GPUs and AI accelerators, optimizing for PPA while guiding cross-functional teams.
SoC Verification Architect / SoC Testbench Architect
Designs and leads verification architecture for complex SoCs with GPU, DSP, and AI accelerators using SystemVerilog, UVM, and coverage-driven methods.
R&D Engineer IC Design 5
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
Security IP Design Engineer
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and SystemVerilog.
Senior SoC Design Verification Engineer
Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.
Security IP Verification Engineer
Design and verify security IP for SoCs, focusing on cryptography, key management, secure boot, and hardware root of trust using UVM, SystemVerilog, and C.
STAFF ASIC Design Engineer
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Staff Design Verification Engineer – SoC and eFPGA
Design and run verification environments for next-gen eFPGA and SoC IP using UVM, SystemVerilog, and assertions to ensure silicon tape-out quality.
Lead FPGA Engineer
Lead the design, testing, and integration of FPGA firmware for high-performance imaging systems, collaborating with hardware and software teams to meet manufacturing requirements.
FPGA Engineer (eInfochips Inc)
Design and maintain FPGA prototyping platforms (HAPS/Xilinx) and write C/C++ firmware tests for SoC verification, debugging silicon bring-up issues in the lab.
Senior RTL Design Engineer, TPU
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
Senior Product Planning Engineer - Simulation, Security, and Deployment
Lead the roadmap for AMD’s FPGA/SoC simulation tools (UVM, SystemVerilog, HDL), RTL encryption, and deployment workflows, shaping verification methodologies and influencing industry standards.