SoC Verification Architect / SoC Testbench Architect
Summary
Designs and leads verification architecture for complex SoCs with GPU, DSP, and AI accelerators using SystemVerilog, UVM, and coverage-driven methods.
๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฐ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ด๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฐ๐ฌ-๐ด๐ฌ ๐๐ฃ๐)
Experience: 10+ yrs
Location: Bengaluru
Job Type: Full-time
We are seeking an experienced SoC Verification Architect / SoC Testbench Architect to lead the verification architecture and strategy for complex System-on-Chip (SoC) designs featuring GPU, DSP, multimedia, image processing, and AI accelerator subsystems. This role is ideal for a verification expert with deep expertise in SystemVerilog, UVM, and coverage-driven verification who is passionate about building scalable verification environments and delivering high-quality silicon.
As a SoC Verification Architect, you will define end-to-end verification methodologies, architect reusable verification frameworks, and collaborate closely with architecture, RTL, firmware, and validation teams to ensure verification completeness through tape-out. You will also mentor engineering teams, establish verification best practices, and drive continuous improvements in verification productivity and quality.
Requirements
Key Responsibilities
- Define and drive the overall verification architecture, methodology, and strategy for complex SoC designs.
- Architect reusable, scalable, and high-performance SystemVerilog/UVM verification environments.
- Develop reusable verification IP (VIP), scoreboards, assertions, checkers, coverage models, and testbench infrastructure.
- Create comprehensive verification plans for block, subsystem, and SoC-level validation while establishing measurable coverage and quality goals.
- Lead verification of GPU, DSP, multimedia, AI accelerator, and other high-performance signal-processing subsystems.
- Validate cache coherency, memory hierarchy, interconnects, QoS, power management, and data integrity across the SoC.
- Drive functional coverage closure, regression automation, and continuous improvements to verification methodologies and infrastructure.
- Collaborate with architecture, RTL, firmware, physical design, and validation teams to resolve verification challenges and ensure successful project execution.
- Lead technical reviews, mentor verification engineers, and promote engineering best practices across the verification team.
- Support verification sign-off activities and ensure tape-out readiness by meeting established quality and coverage metrics.
What Makes You a Great Fit
- 10+ years of experience in ASIC/SoC Verification with a strong track record of leading complex verification programs through tape-out.
- Deep expertise in SystemVerilog, UVM, SystemVerilog Assertions (SVA), Functional Coverage, and Coverage-Driven Verification methodologies.
- Proven experience architecting reusable, scalable verification environments and testbench frameworks.
- Strong understanding of SoC architecture, subsystem integration, and advanced verification methodologies.
- Hands-on experience verifying GPU, DSP, multimedia, image/video processing, AI accelerator, or other compute-intensive subsystems.
- Solid knowledge of AMBA protocols (AXI, AHB, APB, CHI), cache coherency, memory hierarchy, DDR, PCIe, USB, Ethernet, and NoC verification.
- Excellent debugging, root-cause analysis, and problem-solving skills with the ability to resolve complex verification challenges.
- Experience driving regression automation, verification infrastructure development, and coverage closure initiatives.
- Strong leadership, mentoring, and cross-functional collaboration skills with the ability to guide technical teams and deliver high-quality verification solutions.
- A proactive mindset with a passion for engineering excellence, scalable verification methodologies, and successful silicon delivery.