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Sr. ASIC Design Verification Engineer (Silicon Engineering)
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring satellite and ground infrastructure connectivity through pre- and post-silicon validation.
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring chips meet performance and reliability needs for global satellite and ground infrastructure.
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Designs and implements advanced ASIC/SOC chips for SpaceX’s Starlink network, focusing on physical design flows, timing closure, and signoff checks to enable global satellite internet connectivity.
Principal Design Verification Engineer (Silicon Engineering)
Principal Design Verification Engineer at SpaceX to develop and verify next-generation ASICs for Starlink satellites and ground infrastructure, ensuring high-performance connectivity in space and global networks.
Principal Design Verification Engineer (Silicon Engineering)
Principal Design Verification Engineer at SpaceX designs, verifies, and validates next-generation ASICs and FPGAs for Starlink’s satellite and ground infrastructure, ensuring high-performance connectivity.
Manager, ASIC Design Engineering (Starshield Silicon)
Lead a team designing ASICs and FPGAs for SpaceX’s Starshield satellite systems, overseeing RTL implementation, verification, and silicon bring-up to deliver high-speed data processing for national security missions.
Physical Design Engineer II (Silicon Engineering)
Designs and implements next-generation ASICs for SpaceX's Starlink network, focusing on physical design steps like synthesis, floorplanning, and place-and-route using industry-standard EDA tools.
Physical Design Engineer II (Silicon Engineering)
Designs and implements next-generation ASICs for SpaceX’s Starlink network, focusing on physical design steps like synthesis, floorplanning, and timing closure to enable global satellite internet connectivity.
Principal ASIC Design Engineer (Starshield)
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog and collaborating with verification and physical implementation teams.
Sr. ASIC Design Engineer (Starshield)
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog, EDA tools, and collaborating with verification and physical implementation teams.
FPGA/ASIC Design Engineer (Silicon Engineering)
Designs and optimizes FPGAs and ASICs for SpaceX's Starlink network, using Verilog/SystemVerilog and collaborating with cross-functional teams to enhance satellite and ground infrastructure performance.
RTL Design Engineer (Silicon Engineering)
Designs and implements FPGAs and ASICs for SpaceX's Starlink network using Verilog/SystemVerilog, collaborating across teams to enhance satellite and ground infrastructure connectivity.
Sr. RTL Design Engineer (Silicon Engineering)
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade silicon for global connectivity.
Sr. RTL Design Engineer (Silicon Engineering)
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade chips that enable global broadband connectivity.
DFT (Design For Test) Lead (6251)
itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable,…
AI Silicon, Junior Digital Design Engineer
Junior Member of Technical Staff - AI Silicon Digital Design Engineer About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental…
AI Silicon, Digital Design Engineer
About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand…
AI Silicon, Design Verification
About Unconventional: Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented…
DFT RTL Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Digital Design Engineer
Designs and implements PCI Express IP blocks in Verilog/SystemVerilog for AMD’s server, client, GPU, and semi-custom chips, collaborating across RTL, verification, and post-silicon bring-up.