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5G Test Automation Engineer
Build and maintain automated test suites for Nokia’s 5G fixed wireless access devices using Robot/Python, validating performance, security, and stability in a Linux-based CI/CD pipeline.
Mixed Signal Design Verification Engineer
Verify mixed-signal IPs (e.g., PCIe, USB4/Type-C PHYs) using SystemVerilog/UVM, EDA tools, and scripting to ensure performance and reliability before silicon tape-out.
Senior Network Engineer_Contract
Designs and deploys secure, high-availability networks for air-traffic and mission-critical systems, leading small teams through integration, testing, and deployment.
Principal Firmware Engineer
Principal Firmware Engineer in Luton designing and auto-generating firmware for complex digital systems using MATLAB, Simulink, Verilog, and FPGA tools.
Physical Design Engineer Intern
Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Front-End Integration Engineer
Build and maintain CI pipelines for ASIC front-end integration, automating EDA tools with Python/Tcl/Shell and managing Perforce streams for hardware silicon development.
Principal COE Digital Design Engineer
Principal engineer designing and verifying PCIe/CXL IP subsystems in SystemVerilog for Marvell’s custom SoCs powering hyperscale cloud and AI data centers.
Senior Staff Design Engineer - Memory Subsystem COE
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Ingénieur principal en analogique/ Principal Engineer - Analog Design
Design, simulate, and validate high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, I/O interfaces) for SoC timing products using Cadence tools and Verilog-A.
Principal DSP Firmware Engineer
Principal firmware engineer designing DSP algorithms and embedded C/C++ code for ultra-low-jitter timing SoCs used in 5G, IoT, and autonomous vehicles.
Principal Engineer - Design
Principal Design Engineer at Microchip Technology leading hardware/firmware co-development and pre/post-silicon verification using emulators and FPGA platforms for SoC devices.
Senior Design Engineer - Security IP
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Staff Physical Design Engineer, HBM
Designs and optimizes physical layouts for high-bandwidth memory (HBM) chips, focusing on floorplanning, power integrity, and signoff using Cadence/ Synopsys tools.
Staff FPGA Design Engineer
Staff FPGA Design Engineer leading architecture, RTL development, verification, and flight-readiness of FPGA-based avionics subsystems for satellites using SystemVerilog/VHDL, Microchip Polarfire, and AMD Zynq/Versal FPGAs.
FPGA Engineer
Designs and verifies FPGA-based digital circuits for automated trading systems, develops reusable IP, and integrates hardware with software stacks using SystemVerilog/Verilog/VHDL and C++.
Senior FPGA Design Engineer / Hardware Engineer
Design and optimize FPGA systems to reduce latency and boost throughput for a proprietary trading firm, using SystemVerilog and automated verification.
Microprocessor VLSI Physical Design Engineer
Design high-speed VLSI circuits for next-gen CPUs, optimizing power, performance, and area while collaborating across teams to solve complex hardware challenges.
Silicon Design Engineer
Design and validate DSP and linear-algebra IP blocks for AMD FPGAs and AI Engine arrays using HDLs and C/C++.
Engineering - Test Engineer
Validates FPGA-based power analysis tools by running tests, collecting data, and automating regression workflows using Python, TCL, and Vivado/Vitis.