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Senior Physical Design Architect – FPGA Backend
Senior Physical Design Architect at Altera to implement FPGA/SoC backend flows from RTL to GDSII, optimizing performance, power, and area while improving PD automation.
Systems and Test Integration Engineer - FPGA Integration & Verification
Design and verify FPGAs for spacecraft test infrastructure, bridging hardware interfaces and enabling real-time functions like packet timestamping and command scheduling.
System Software Engineer, Embedded (Diagnostics)
Develop low-level diagnostics and system software for an AI inference platform, including firmware, drivers, and Linux kernel modules, while collaborating with hardware teams on bring-up and optimization.
Test Engineer
Develops and maintains automated test systems for life-science instruments, troubleshooting hardware/software issues during mass production and new-product introduction.
Staff Engineer, Physical Design
Design and optimize high-performance processor chips using advanced EDA tools, focusing on synthesis, place-and-route, timing closure, and ECOs for server, 5G/6G, and networking applications.
Senior FPGA Engineer (VHDL/Verilog)
Designs and optimizes VHDL/Verilog hardware components for networking systems (SmartNICs, optical switches), writes test cases in Python, performs timing analysis, and collaborates with software/networking teams on system-level debugging.
CAD Developer, IR, Timing and Physical Design Optimization
Develop and optimize C++ algorithms for IR drop, timing, and physical design to improve chip performance and power efficiency in advanced VLSI flows.
FPGA Compiler (Placer) Engineer
Develop and optimize FPGA placement algorithms to improve timing, power efficiency, and design quality within Altera’s compiler toolchain.
AI-Driven ASIC Physical Design Principal Engineer
Principal engineer builds AI-driven EDA workflows to automate ASIC physical design, using LLMs and agentic tools to reduce design cycles and improve timing/congestion outcomes.
Principal Logic Design Engineer
Principal Logic Design Engineer Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our…
Lead Physical Design Engineer
Lead the physical design of high-performance chip IP blocks using Cadence Innovus, focusing on floorplanning, place-and-route, timing closure, and manufacturability sign-off.
Salesforce Developer
A Salesforce developer builds, configures, and maintains Salesforce CRM solutions (e.g., Sales, Service Cloud) using Apex, Lightning Web Components (LWC), and Flow, ensuring seamless integration for sales, marketing, and customer service teams.
DFT Design Engineer
Lead a team designing and automating Design-for-Test (DFT) features for complex ASICs, GPUs, and APUs using Perl, Python, TCL, and AI/ML tools.
Design Verification Engineer
Design Verification Engineer at AMD builds and maintains tests to verify complex processor IP, debug failures, and collaborate with RTL and firmware teams to ensure high-quality silicon designs.
Silicon Design Engineer
Designs and implements DFT/DFD features for AMD’s ASICs (APUs, GPUs, game consoles) while automating workflows via Python/Perl/TCL scripts and debugging CAD/IP regressions.
Silicon Design Engineer, Design Automation
Design engineer optimizing RTL-to-GDS flows for AMD’s chip projects, scripting tool flows in TCL/Python, and collaborating with global teams on synthesis, place-and-route, and physical signoff.