Tech jobs

C - Focused Design Verification Engineer

Open 19d North America

assembly cpp python systemverilog verilog

Designs and implements C-based tests for wireless SoC verification and power analysis, collaborating across chip disciplines to ensure functional silicon for Apple products.

SK Hynix Memory Solution

Open 68d North AmericaStaff

Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)

ai cloud machine-learning perl python +2 skills

Designs and verifies high-speed interface IP for next-gen storage subsystems (NVMe/Chiplet) in ASICs, leading RTL development through silicon bring-up for enterprise and AI data center storage solutions.

Open 69d North AmericaPrincipal H-1B sponsor history

Principal Design Verification Engineer

ai cpp ethernet networking pcie +3 skills

Principal Design Verification Engineer at Astera Labs designs and verifies advanced ASICs for AI infrastructure using SystemVerilog, UVM, and scripting languages, ensuring robust connectivity solutions for server and networking applications.

185 000 – 230 000 $

Open 69d On-siteNorth AmericaPrincipal H-1B sponsor history

Principal Physical Design Engineer, STA

ai automation cloud ethernet networking +6 skills

Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.

209 000 – 250 000 $

Open 69d MENASenior H-1B sponsor history

Senior ASIC Design Engineer

Israel

Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.

ai automation ethernet pcie perl +3 skills

Open 69d North AmericaSenior H-1B sponsor history

Senior Digital Design Engineer, IP and Methodology

ai automation ethernet networking pcie +2 skills

Designs and implements high-performance digital circuits for AI connectivity chips, focusing on CPU subsystems and security features, using SystemVerilog and industry-standard EDA tools.

135 000 – 195 000 $

Open 69d MENAPrincipal H-1B sponsor history

Staff/ Principal Design Verification Engineer

Israel

Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.

ai ethernet networking pcie python +2 skills

Open 35d MENAPrincipal H-1B sponsor history

Staff / Principal ASIC Design Engineer

Israel

Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.

ai automation ethernet pcie perl +3 skills

Google

Systems Design Engineer, Digital Signal Processing

North America

signal-processing systemverilog verilog

Systems Design Engineer, Digital Signal Processing _corporate_fare_ Google _place_ Sunnyvale, CA, USA Advanced Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders;…

Cadence Design Systems

North AmericaFull-timePrincipal

Principal Design Engineer

cpp fpga pcie prototyping systemverilog +1 skills

Sr Principal Design Engineer Location: SAN JOSE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our North America…

Cadence Design Systems

ai automation cpp ethernet linux +6 skills

Principal Design Engineer

APACFull-timePrincipal

China

Sr Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Joining our Palladium…

Ambiq Micro, Inc.

Open 64d North AmericaSenior

Sr. Director - SoC Front End Engineering

ai automation machine-learning systemverilog

Lead the front-end design and verification of ultra-low-power SoCs for edge AI microcontrollers, optimizing CPU subsystems, neural accelerators, and security while scaling a high-performing engineering team.

Ambiq Micro, Inc.

Open 64d North AmericaStaff

Sr. Staff Engineer - Digital Design Verification

ai automation cpp machine-learning perl +3 skills

Senior engineer who designs and runs verification tests for low-power System-on-Chip designs used in IoT and edge-AI products, using SystemVerilog, UVM, and C/C++.

180 000 – 250 000 $

Ambiq Micro, Inc.

ai cpp perl python systemverilog +2 skills

Staff Engineer - Design Verification

Open 49d APACStaff

Singapore

Design verification engineer at Ambiq Micro, Singapore, responsible for verifying low-power SoCs for IoT applications using SystemVerilog/UVM, ARM/RISC-V, and power-aware methodologies.

Virtu Financial

On-siteNorth AmericaInternshipIntern

Hardware Engineer Intern

cpp fpga python systemverilog verilog

Intern designs FPGA/ASIC solutions for ultra-low-latency trading systems, writing and verifying RTL in SystemVerilog and bringing designs up on live hardware.

Western Digital

Open 19d HybridNorth AmericaInternshipIntern

Summer 2027 Intern - Hardware Engineering

ai analytics assembly automation cad +16 skills

Design and verify custom silicon chips for next-generation data storage hardware, using RTL, Verilog/SystemVerilog, and digital logic while collaborating with cross-functional engineering teams.

Western Digital

Open 19d RemoteNorth America

Hardware Engineer

ai analytics assembly automation cad +16 skills

Design and verify custom silicon and hardware for next-generation data storage devices, collaborating across ASIC, firmware, and systems engineering teams using RTL, Verilog, and embedded C/C++.

Advanced Micro Devices, Inc

AI/ML Silicon Verification Solutions Engineer – Tools

Open 19d North America

agentic-ai ai automation aws azure +20 skills

Build AI-powered tools to automate and enhance semiconductor verification workflows, using Python, LLMs, and cloud DevOps for faster, smarter hardware development.

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