Hardware Engineer Intern
Posted Updated 6
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Summary
Intern designs FPGA/ASIC solutions for ultra-low-latency trading systems, writing and verifying RTL in SystemVerilog and bringing designs up on live hardware.
You will work across the hardware design lifecycle, from architecture and RTL implementation through simulation, verification, and bring-up on live hardware. You will tackle ultra-low-latency trading engineering challenges with guidance from experienced engineers.
Responsibilities
- Design FPGA and ASIC solutions
- Develop hardware architecture and implement RTL
- Simulate and verify hardware designs
- Bring up designs on live hardware
- Tackle ultra-low-latency engineering challenges
Requirements
- Be currently pursuing a Masters Degree in Electrical Engineering or a related field
- Have experience with Hardware Description Languages, including SystemVerilog and Verilog
- Be comfortable programming with Python, C++, or similar languages
- Demonstrate a basic understanding of network protocols
- Demonstrate strong problem-solving and communication skills
Benefits
- Onsite gym and workout classes
- Onsite barista
- Weekly happy hours and social events
- Breakfast and lunch
- Transportation
