Tech jobs

Staff RTL Design Engineer

APACStaff

SOC Engineering, Staff Engineer - RTL Design Location: Noida, India Job Title: RTL Design Engineer, Staff Level - SoC Design We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling…

ai systemverilog verilog

silabs

Manager / Senior Manager – Design Verification

Open 21d APACSenior

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Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC solutions for edge connectivity applications.

NXP Semiconductors

Open 21d APACStaff Licensed NL sponsor

Staff Digital Design Engineer

ethernet networking systemverilog verilog

Lead architecture and RTL design for Automotive Ethernet PHY subsystems, implementing PCS pipelines, safety mechanisms, and ISO 26262-compliant logic in Verilog/SystemVerilog.

Marvell

Open 21d APACFull-timePrincipal

Principal Engineer, Design Verification

Vietnam

Principal Engineer in Marvell’s Design Verification team, building and running testbenches to verify high-speed storage IP like read channels and cryptographic engines using SystemVerilog/UVM and EDA tools.

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Marvell

Open 21d APACFull-timeStaff

Design Verification (Staff to Senior Staff Engineer)

Vietnam

Design verification engineer building and running testbenches for high-speed storage IP (HDD/SSD) using SystemVerilog/UVM and collaborating with SoC teams to debug complex digital designs.

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Intel

Open 19d HybridNorth America

Design Verification Architect

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Architects and implements pre-silicon verification strategies using UVM or formal methods, builds testbenches, and integrates block-level tests into chip-level environments for Intel hardware designs.

164 470 – 232 190 $

Inversion

Open 65d North AmericaFull-timeSenior

Senior Avionics Embedded Software Engineer

automation ci-cd cpp embedded-software ethernet +14 skills

Develops and maintains safety-critical embedded flight software in C/C++ for spacecraft avionics, integrating with microcontrollers and real-time systems to support hypersonic reentry operations.

139 000 – 201 000 $

Amazon

Software Development Engineer, Post Silicon Validation

North America

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- Bachelor's degree or above in computer science, electrical engineering, or related field - - 3+ years of hands-on post-silicon validation or system validation engineering experience - - Strong programming skills…

Optiver

FPGA Engineer

Open 65d North America

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Designs and implements high-speed FPGA-based trading systems to accelerate network infrastructure and trading components, working closely with traders and software engineers.

200 000 – 200 000 $

Optiver

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FPGA Engineer

Open 65d Europe

Netherlands

Designs and implements low-latency hardware trading systems using FPGAs and ASICs, collaborating with traders and software engineers to solve complex financial market problems.

Optiver

FPGA Engineer

Open 68d North America

cpp fpga machine-learning systemverilog verilog +1 skills

Designs and optimizes FPGA-based hardware for ultra-low-latency trading systems, coding in VHDL and collaborating with software teams to enhance market-making infrastructure.

200 000 – 200 000 $

Google

ai cloud cpp ethernet fpga +8 skills

Micro-Architect, Networking, Google Cloud

Open 22d MENA

Israel

Designs and leads the development of networking ASICs and subsystems for Google's custom silicon, focusing on RTL coding, verification, and physical design to power high-performance hardware.

Graphcore

Open 68d UK Licensed UK sponsor

Director, Silicon Logical Design

United Kingdom

Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.

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Graphcore

Open 42d UKPrincipal Licensed UK sponsor

Staff/Principal Logical Design Engineer

United Kingdom

Designs and implements micro-architecture and RTL for AI chips, collaborating with cross-functional teams to deliver high-quality silicon solutions using SystemVerilog/VHDL and EDA tools.

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Graphcore

Open 34d APACStaff Licensed UK sponsor

Staff Silicon Logical Design Engineer - Bengaluru, Multiple Vacancies

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Designs and integrates advanced semiconductor logic for AI chips in Bengaluru, using SystemVerilog, Python, and digital design flows to deliver RTL and microarchitecture for Graphcore’s silicon.

CAD RTL/DV Infrastructure Engineer

APAC

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CAD RTL/DV Infrastructure Engineer, Sr Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…

Staff CAD RTL/DV Infrastructure Engineer

APACStaff

airflow analytics automation bash cad +9 skills

CAD RTL/DV Infrastructure Engineer, Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…

Lead Engineer, RISC-V Subsystem RTL Design

APACLead

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Lead Engineer/ Staff – RISCV Subsystem RTL Design Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…

Security RTL Design Engineer

APAC