Micro-Architect, Networking, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Lead Design Activities at IP’s, SubSystems(S.S) and SoC.
• Define the block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
• Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power, and FPGA/silicon bring-up, as well as test plan development and coverage analysis for block and SOC-level verification.
• Communicate and collaborate with multi-disciplined and multi-site teams.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience architecting networking ASICs from specification to production or equivalent experience.
• 4 years of experience in technical leadership.
• Experience developing RTL for ASIC subsystems.
• Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
• Experience in Micro-Architecture, RTL Design, Verification, Design Quality checks, Physical Design aspects of RTL coding, and Power.

Preferred qualifications:

• Experience architecting networking switches, end points, and hardware offloads.
• Experience working with design networking: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
• Experience working with software teams optimizing the hardware/software interface.
• Familiarity with Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
• Proficiency in a procedural programming language (e.g., C++, Python, Go).
• Knowledge of TCP, IP, Ethernet, PCIE and DRAM.