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GPU Cluster Architect
Designs, validates, and deploys large-scale GPU clusters for an AI-infra startup, negotiating with CSPs and vendors to ensure optimal power, cooling, and high-speed networking for AI workloads.
Platform Hardware Engineer, Data Center Accelerator Platforms
Design and validate next-gen accelerator boards for AI/ML/HPC using Openchip silicon, spanning schematic reviews, PCB layout, bring-up, validation, and system integration.
RTL IP Design Engineer
Designs and verifies RTL IP blocks for networking solutions, collaborating with architects and physical design teams to ensure first-pass silicon success.
FPGA Emulation Engineer
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
Intern, Firmware Engineering
Intern in firmware engineering designing, testing, and maintaining C++/Python code for storage devices with SAS/SATA/PCIe interfaces and embedded systems.
Engineer, Firmware Engineering
Develops and maintains firmware for hard drives using C++, Python, and embedded systems, ensuring compatibility with SAS, SATA, and PCIe interfaces.
Hardware Engineer
Design and develop high-performance NAS and enterprise storage hardware, including PCB schematics, power delivery, and system validation with PCIe, NVMe, and Ethernet interfaces.
Hardware Engineer
Designs and validates high-speed Ethernet hardware for enterprise switches, including schematics, PCB layout, signal integrity, and system bring-up.
Design Verification Engineer
Verify and validate AMD’s next-gen GPU and SOC designs using Verilog/SystemVerilog, UVM, and emulation platforms like Veloce/Zebu to ensure functional correctness and performance.
Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
Architect high-speed interconnect subsystems (PCIe, CXL, UA Link) for next-gen SoCs, defining coherent/non-coherent communication architectures across mobile, automotive, datacenter, and IoT markets.
Principal Software Engineer - Embedded (RIS)
Build low-level embedded software and drivers for next-gen networking platforms, programming NPUs/ASICs and enabling high-performance routing systems in Linux environments.
Principal Digital Hardware Design Engineer - Computing Products (Remote)
Principal Electrical Engineer designing ruggedized avionics hardware for aircraft, including mission computers and video processing modules, with a focus on high-speed digital design and EMI control.
Principal / Senior Hardware (Electrical) Engineer – Optical Networking & High-Speed Systems
Lead hardware design for next-gen optical networking and high-speed communication systems, collaborating across teams to develop and validate cutting-edge networking hardware.
SoC Verification Architect / SoC TB Architect
Leads verification architecture for complex SoCs using SystemVerilog/UVM, driving tape-out readiness for advanced compute subsystems like GPUs and AI accelerators.
SoC Verification Architect / SoC Testbench Architect
Designs and leads verification architecture for complex SoCs with GPU, DSP, and AI accelerators using SystemVerilog, UVM, and coverage-driven methods.
Lead SoC Architect
Define architecture and technical strategy for next-generation semiconductor products, collaborating with hardware/software teams to ensure high-performance, power-efficient solutions from concept to silicon validation.
R&D Engineer IC Design 5
Design and verify high-performance network switch ASICs using SystemVerilog, UVM, and C++, developing complex verification environments and test plans.
Senior SoC Design Verification Engineer
Leads SoC-level verification for a semiconductor company’s edge AI processor (GPNPU), designing testbenches, verifying subsystems (NoC, PCIe/UCIe, DDR), and ensuring hardware-software co-simulation coverage using UVM, Verilog, assembly, and Python.
STAFF ASIC Design Engineer
Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.