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Principal Application Software Engineer
Principal software engineer at Oracle designing, debugging, and testing database and server systems using languages like C/C++, Python, and SQL, with a focus on hardware-software integration in supply chain operations.
Physical Design Engineer
Designs and implements high-performance ASICs from RTL to GDSII for advanced process nodes (7nm–2nm), ensuring timing, power, and area goals are met.
Software Engineer II
Develops formal verification IP for hardware design using Verilog and SystemVerilog Assertions, focusing on industry-standard bus protocols like AXI or PCIe.
Senior Staff Engineer, Digital IC Design
Designs, verifies, and implements RTL for power management ICs and SoCs, collaborating with architects and verification teams to deliver high-performance semiconductor solutions.
Senior Principal Design Verification Engineer
Lead verification of high-performance SRAM memory compilers and subsystems for Marvell’s chip IP, using UVM, C, and industry tools to ensure correctness and performance before silicon bring-up.
Sales Manager - NCV Finance - Other OEM - Motor Finance - Sales - Nashik - Jay Plaza - JM
Key Deliverables: Lead generation Ensure necessary leads are generated through BDMs and channel partners/open market Customer relationship management Develop and maintain relationship with existing and potential…
Senior Engineer I - Physical Design
Designs and optimizes low-power, mixed-signal microcontroller chips from floorplan to GDSII tapeout using EDA tools like Innovus and Calibre.
Senior Engineer II - Physical Design
Designs and implements physical layouts for large system-on-chip (SoC) designs, using tools like Innovus/ICC2 to ensure timing closure and physical verification for chips from 40nm down to 3nm and below.
Director, SOC Design
Leads a global team to architect, design, and deliver complex multi-chiplet System-on-Chip (SoC) designs for enterprise and AI infrastructure, using RTL coding, IP integration, and verification flows.
Senior Digital ASIC Design Engineer
Designs and implements digital ASICs for scientific instruments, focusing on low-power, radiation-aware systems for particle detectors and high-energy physics applications using SystemVerilog/Verilog and EDA tools.
Senior Front End Design Engineer (Microarchitecture) - Sunnyvale HQ
Designs and develops high-performance semiconductor architectures for AI chips, focusing on RTL design, integration, and collaboration with verification and software teams.
ASIC Design Engineer
Designs and implements high-speed interconnect ASICs, writing RTL and firmware to integrate CPU IP, AMBA fabrics, and optical control loops, then driving synthesis, timing closure, emulation, and silicon bring-up.
Solutions Architect I
Designs and demonstrates IT network monitoring solutions for enterprise clients, troubleshooting and customizing systems while collaborating with sales and technical teams.
RTL Design Engineer
Designs and implements digital logic and IP for AI chips or SoCs using Verilog/SystemVerilog, verifies functionality, and integrates IP into larger systems with front-end design flows.
Principal Silicon Design Engineer (Design Automation)
Leads the full-chip integration methodology for FPGA and custom SoC programs, defining how IP, power, and signoff corners are integrated and verified across projects.
Custom Circuit Design (Sr. Staff / Principal)
Role Overview As a Sr. Staff/Principal Custom Circuit Design Engineer at Velaura AI, you will lead the architecture, design, and optimization of high-performance, low-power standard cell libraries and custom digital…
DFT Engineer (Architect / Manager / Sr. Manager)
Role Overview As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high-performance computing…
Physical Design Engineer (Staff / Sr. Staff / Principal)
Role Overview As a Staff/Sr. Staff/Principal Physical Design Engineer at Velaura AI, you will be responsible for driving the physical implementation and sign-off of critical blocks for next-generation AI and…
Digital Design SME
Responsibilities In this role, the Digital Design SME will act as a Technical Advisor/Consultant to critical SI/SETA activities and serve as a primary interface between the Program customers/stakeholders, the technical…
Physical Design Engineer - Flow & Methodologies
Designs and automates the RTL-to-GDSII physical design flow for AI inference hardware, optimizing power, performance, and area while ensuring signoff compliance.