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Graduate - Design Verification Engineer
This graduate role involves working with verification experts to verify DDR subsystems using SystemVerilog, UVM, and formal verification techniques. The engineer will write tests, develop testbench components, and track verification quality metrics like code and functional coverage.
Senior Staff SOC DFX RTL Design Engineer
Senior Staff SOC DFX RTL Design Engineer at AMD's Radeon Technologies Group responsible for planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) for next-generation microprocessors, collaborating with architecture, IP design, and physical design teams.
RTL Design Manager
Leads a team designing high-performance, low-power System-on-Chip (SOC) components using Verilog/System Verilog, UPF, and industry-standard EDA tools.
Senior RTL design engineer - SOC Intergration
RTL/SOC integration design engineer at AMD Hyderabad, responsible for ASIC design in sub-20nm nodes using Verilog/SystemVerilog, timing analysis, low-power design, and SOC verification tools.
Sr. Staff ASIC Design Engineer
Sr. Staff ASIC Design Engineer responsible for microarchitecture and RTL design of high-performance AI inference ASICs using Verilog/SystemVerilog, integrating CPU and third-party IPs, and collaborating with physical design and verification teams.
Senior FPGA Engineer
Senior FPGA Engineer leading RTL design and FPGA development for spaceborne radar systems, working with Verilog/VHDL, synthesis, place-and-route, and timing analysis on FPGA/SoC platforms.
Desenvolvedor(a) full stack sênior | node.js + react.js
Senior Full Stack Developer building and evolving microservices and APIs using Node.js, NestJS, React.js, and TypeScript in a 100% remote PJ role at a headhunting/coaching firm.
Sr. AI/ML Engineer
This role involves developing and scaling an AI-assisted silicon design framework using agentic ecosystems, RAG, and LLM orchestration. The engineer will build production-ready AI workflows to automate and optimize the silicon IP development lifecycle.