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Lead Logic Design Engineer
Lead MTS Logic Design Location: Vught, UNAVAILABLE, NL Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design…
Logic Design Engineer
SMTS Logic Design Location: Montreal, UNAVAILABLE, CA Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of…
Design Verification Engineer, PCIe Controller
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Hardware Security Engineer
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Software Development Engineer
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
Senior FPGA Prototyping Engineer
Senior FPGA engineer builds FPGA-based prototypes and validation platforms to accelerate ASIC development for next-gen communications and satellite hardware, enabling early software/firmware integration and silicon bring-up.
VLSI Design Engineer
We are looking for talented and experienced VLSI Design Engineers/Micro-architects. As an VLSI Digital Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new…
Senior Engineer - Frontend CAD
Build and optimize front-end CAD methodologies and verification flows for Ericsson’s 5G/6G ASICs and FPGAs using SystemVerilog/UVM, EDA tools, and CI pipelines, with a focus on AI-driven automation.
Staff Design Verification Engineer
Design verification engineer building and running SystemVerilog/UVM testbenches to validate DDR5, LPDDR5/6, and DFI memory interfaces for AMD’s server products.
RTL Designer – Physical AI Compute
Design and optimize RTL for AI-focused System-on-Chip components, focusing on performance, power, and area while collaborating on verification and physical design.
Digital Design Engineer, HBM
Design and verify high-bandwidth memory (HBM) digital logic using Verilog/SystemVerilog, collaborating with verification and physical-design teams to ensure robust closure and post-silicon debug.
Principal FPGA Engineer - Markets Technology
Senior FPGA engineer designing ultra-low-latency hardware accelerators for an exchange’s trading platform, setting standards and mentoring teams.
CPU Design Verification Engineer
Verify CPU design correctness by writing test plans, assembly/C tests, and coverage monitors; collaborate with architects and RTL designers to ensure functional accuracy before mass production.
FPGA Engineer Intern
Build ultra-low-latency FPGA/ASIC components for a global market-making engine, coding in SystemVerilog and Python and seeing designs run on real hardware.
Principal FPGA Engineer - Markets Technology
Lead FPGA design and hardware acceleration for low-latency trading systems, defining architectures for market connectivity and protocol processing to optimize performance and deterministic behavior.
Semiconductor Software Engineer
Build low-level software and tooling for semiconductor design, verification, and post-silicon validation, including drivers, EDA infrastructure, and data pipelines.
Staff Design Verification Engineer
Design verification engineer building and running SystemVerilog/UVM testbenches for DDR5/LPDDR5 memory interfaces and DFI protocols in AMD’s server products.
Principal Staff Silicon Design Engineer - DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware features.