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Senior Engineer - Frontend CAD
Build and optimize front-end CAD methodologies and verification flows for Ericsson’s 5G/6G ASICs and FPGAs using SystemVerilog/UVM, EDA tools, and CI pipelines, with a focus on AI-driven automation.
Staff Design Verification Engineer
Design verification engineer building and running SystemVerilog/UVM testbenches to validate DDR5, LPDDR5/6, and DFI memory interfaces for AMD’s server products.
RTL Designer – Physical AI Compute
Design and optimize RTL for AI-focused System-on-Chip components, focusing on performance, power, and area while collaborating on verification and physical design.
Principal/Staff Design Verification Engineer
Leads verification strategy for complex IC designs, guiding teams to build test environments, debug RTL, and improve coverage using UVM, SystemVerilog, and RISC-V protocols.
Digital Design Engineer, HBM
Design and verify high-bandwidth memory (HBM) digital logic using Verilog/SystemVerilog, collaborating with verification and physical-design teams to ensure robust closure and post-silicon debug.
Senior Design Verification Engineer
Designs and runs verification tests for next-gen DRAM and memory chips using SystemVerilog/UVM, debugging complex hardware issues and automating verification workflows.
Principal Design Verification Quality Engineer
Lead DRAM verification quality and methodology, defining AI-enabled workflows and scalable test systems to improve coverage, traceability, and defect prevention across Micron’s DRAM roadmap.
Principal FPGA Engineer - Markets Technology
Senior FPGA engineer designing ultra-low-latency hardware accelerators for an exchange’s trading platform, setting standards and mentoring teams.
CPU Design Verification Engineer
Verify CPU design correctness by writing test plans, assembly/C tests, and coverage monitors; collaborate with architects and RTL designers to ensure functional accuracy before mass production.
FPGA Engineer Intern
Build ultra-low-latency FPGA/ASIC components for a global market-making engine, coding in SystemVerilog and Python and seeing designs run on real hardware.
Principal FPGA Engineer - Markets Technology
Lead FPGA design and hardware acceleration for low-latency trading systems, defining architectures for market connectivity and protocol processing to optimize performance and deterministic behavior.
Semiconductor Software Engineer
Build low-level software and tooling for semiconductor design, verification, and post-silicon validation, including drivers, EDA infrastructure, and data pipelines.
Staff Design Verification Engineer
Design verification engineer building and running SystemVerilog/UVM testbenches for DDR5/LPDDR5 memory interfaces and DFI protocols in AMD’s server products.
Principal Staff Silicon Design Engineer - DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware features.
Amazon ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Design and optimize custom ASICs for AWS’s machine-learning servers, focusing on high-performance, power-efficient SystemVerilog RTL and trade-offs between features, power, and area.
Senior Hardware (FPGA) Engineer
Design and implement high-performance FPGA logic for embedded machine-vision systems, including RTL coding, simulation, and vendor selection, while collaborating with hardware and software teams.
Senior FPGA Development Engineer
Designs and verifies high-performance FPGA subsystems for network test and measurement hardware using Verilog/SystemVerilog and industry-standard EDA tools.
Principal Engineer - FPGA/ASIC Design
Principal Engineer designing and verifying FPGA/ASIC solutions for Rolls-Royce engine control systems using VHDL/Verilog and DO-254 standards.
Senior CPU Design Verification Engineer
Verify CPU and SoC designs using SystemVerilog/UVM to catch bugs before silicon tape-out, collaborating with architects and RTL teams.