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ASIC Physical Design Engineer
The application window is expected to close on: 08/28/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Acacia, part of Cisco,…
Senior Real Time Market Data C++ Software Engineer (AI Capable) - Vice President
The Real-time Market Data department is part of the Algorithmic Trading Super Department. It is responsible for developing, engineering, deploying and maintaining applications to disseminate and enhance the value of…
Senior Hardware Validation Engineer
Our technology has no boundaries! NVIDIA is building the world’s most groundbreaking and state of the art compute platforms for the world to use. It’s because of our work that scientists, researchers and engineers can…
Physical Design Engineer
Designs and optimizes chip layouts for SoC projects using EDA tools like Genus and Innovus, focusing on performance, power, and physical verification checks.
System Speed and Reliability Co-Design Engineer
SCG sits at the crossroads of design, architecture, marketing, and productization—owning the journey from the architecture stage through final product definition across Gaming, Datacenter, Automotive, and Embedded…
Senior / Physical Design Engineer
Senior Physical Design Engineer responsible for implementing advanced chip layouts (12nm/6nm/4nm) from netlist to GDS, coordinating block-level and full-chip tapeouts using Synopsys/Cadence tools.
Senior Design Automation Engineer
Senior engineer automating and maintaining hardware emulation tools (Cadence Palladium, Xilinx, ARM) to validate implantable cardiac devices and speed up Medtronic’s design flows.
Integrated Circuit Design Verification Engineer
Design and verify integrated circuits for AR display systems, building UVM-based testbenches and using Siemens Questa for simulation and debug.
Tech Enterprise Data Governance - Sr Developer AVP
Description Enterprise Data Governance organization is recruiting a Data Governance Senior Developer to help drive Collibra Data Intelligence platform implementation. As a Senior Developer will collaborate with…
Senior Real Time Market Data C++ Software Engineer (AI Capable) - Vice President
Build and maintain ultra-low-latency C++ systems that process and distribute real-time market data for trading, while integrating AI to automate development, testing, and deployment workflows.
Senior Manager, DFT
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Principal IC Digital Design - SoC Design/Micro-architecture
Principal IC Digital Design Engineer leads SoC micro-architecture, RTL development, and HW/SW co-design for advanced semiconductor solutions used in AI, cloud, and telecom.
Senior FPGA Designer
Designs and implements FPGA logic for optical telecommunication products, collaborating with hardware and firmware teams to validate and optimize high-speed data transmission systems using Verilog/SystemVerilog and AMD/Xilinx or Altera tools.
SoC Modelling Architect
Designs and validates next-generation GPU and SoC architectures using SystemC/TLM, C++, and build tools to model graphics and parallel-compute features for high-performance computing.
Network Engineer, Cloud Support (Perm)
Provide 24/7 operational support for customers' cloud and SDN networks, troubleshooting issues across Azure services like Front Door, DDoS protection, and ExpressRoute.
Infrastructure Support Engineer, Linux (Contract)
Deliver Service Operations support to both internal and external customers in alignment with contractual terms and established Service Level Agreements (SLAs). Maintain and ensure the optimal performance of all systems…
Technical Support Analyst
ASX: Powering Australia's financial markets Why join the ASX? When you join ASX, you’re joining a company with a strong purpose – to power a stronger economic future by enabling a fair and dynamic marketplace for…
Senior/ IC Design Engineer (Design Verification)
Design verification engineer building and running SystemVerilog/UVM testbenches to validate ASIC/SoC designs, using AI-assisted tools to improve coverage and debug efficiency.