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849 jobs
Astera Labs
7 days ago

Soc Design Verification Director

Open 68d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.

ai ethernet firmware fpga machine-learning +6 skills
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Astera Labs
7 days ago

Sr. Principal Program Manager, ASIC Design

Open 67d North AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.

ai asic cad ethernet fpga +6 skills
195 000 – 240 000 CAD
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Astera Labs
7 days ago

IP Design Director

Open 63d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Designs high-performance digital IP for AI connectivity chips, focusing on RTL, synthesis, and integration of processor and peripheral IPs at advanced semiconductor nodes.

ai asic authentication ci-cd ethernet +9 skills
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Astera Labs
7 days ago

SoC Design Director

Open 63d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.

ai asic authentication ci-cd ethernet +9 skills
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Astera Labs
7 days ago

Technical Lead Physical Design Engineer

Open 61d On-siteNorth AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.

ai automation cad cloud ethernet +8 skills
140 000 – 180 000 CAD
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Astera Labs
7 days ago

DFT Design Engineering Director

Open 55d North America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Leads a team to design test strategies for high-speed PCIe switch chips using advanced 2.5D/3D packaging, ensuring manufacturability and quality for AI infrastructure components.

accessibility ai asic assembly ethernet +7 skills
230 000 – 265 000 $
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Astera Labs
7 days ago

Physical Design Engineering, VP

Open 35d North AmericaC-level H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Leads a team to design and tape out advanced multi-die switching chips for AI infrastructure using UCIe, UALink, and PCIe Gen 6/7 in 7nm or smaller process nodes.

ai automation ethernet machine-learning networking +2 skills
250 600 – 375 000 $
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Astera Labs
7 days ago

Distinguished ASIC Design Engineer

Open 29d On-siteEurope H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Germany

Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.

ai asic ethernet firmware hpc +5 skills
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Astera Labs
7 days ago

Senior Principal ASIC Design Engineer

Open 29d On-siteEuropePrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Germany

Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.

ai asic ethernet firmware hpc +5 skills
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Astera Labs
7 days ago

Tech Lead Design Engineer

Open 28d North AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Designs and leads RTL implementation for AI infrastructure silicon, focusing on PCIe, CXL, Ethernet, and emerging interconnects to deliver high-performance connectivity solutions.

ai ethernet pcie rtl systemverilog +1 skills
133 200 – 185 000 $
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Astera Labs
7 days ago

Principal Physical Design Engineer

Open 26d North AmericaPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Leads end-to-end physical design of high-performance AI infrastructure SoCs, owning floorplanning, timing, power, and signoff for advanced process nodes (7nm+) while mentoring engineers and collaborating with RTL, DFT, and analog teams.

ai automation cad ethernet pcie +3 skills
185 000 – 230 000 $
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Astera Labs
7 days ago

Design Verification Engineer (Intern 2026)

Open 79d North AmericaInternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.

ai analytics asic cmos cpp +10 skills
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Advanced Micro Devices, Inc
7 days ago

Lead IP/SoC level design verification

APACLead
India

The Lead IP/SoC Design Verification Engineer will plan and execute verification strategies for AMD's Soft IP cores using UVM, SystemVerilog, and formal verification techniques. The role involves driving verification closure, maintaining CI/CD regression infrastructure, and collaborating with cross-functional teams to ensure high-quality silicon-proven IP.

ai asic automation bash ci-cd +10 skills
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Advanced Micro Devices, Inc
7 days ago

CPU Performance Modelling Architect

UK
United Kingdom

The CPU Performance Modelling Architect develops and maintains cycle-accurate microarchitecture performance simulators to analyze and optimize CPU performance. The role involves collaborating with hardware and software teams to define architectural features and improve performance modeling methodologies.

ai cpp rtl
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Aperio Global
7 days ago

Senior Hardware / Software Design Engineer III with TS/SCI + Poly

Open 55d CISContractSenior
Moldova

Senior HW/SW Design Engineer developing FPGA-based DSP implementations and integrating them with Linux software stacks for RF communication and collection systems in support of national security missions.

ai analytics cloud cloud-native cpp +7 skills
130 000 – 230 000 $
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preference-model Backed by a16z
7 days ago

Member of Technical Staff - Low Level & Kernels Capabilities

Open 40d On-siteNorth AmericaFull-time
United States

Build low-level reinforcement learning environments targeting hardware features like GPUs, FPGAs, and vector ISAs to stress-test AI models, using C/C++/CUDA and Python.

ai anthropic assembly automation cpp +9 skills
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Riverlane
7 days ago

Senior FPGA Engineer - Systems Team

Open 59d UKPart-timeSenior
United Kingdom

Senior FPGA engineer designs and deploys low-latency quantum control systems, integrating FPGA hardware with customer setups and troubleshooting quantum experiments.

cpp ethernet fpga pre-sales python +4 skills
68 000 – 82 000 £
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Advanced Micro Devices, Inc
7 days ago

Staff SerDes Design Engineer

Open 75d UKStaff
United Kingdom

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…

ai asic embedded-systems ethernet networking +4 skills
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Advanced Micro Devices, Inc
7 days ago

Staff Silicon Design Engineer

APACStaff
Singapore

Designs and verifies next-gen ASIC/FPGA SoCs using SystemVerilog/UVM, ensuring bug-free silicon by collaborating across global teams.

ai asic cpp firmware fpga +6 skills
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jobgether
last week

Senior Staff Engineer - Physical Design

RemoteAPACFull-timeStaff
India

Leads end-to-end physical implementation for advanced semiconductor and AI/HPC designs, optimizing PPA and reliability while collaborating with RTL, STA, DFT, and CAD teams to drive tape-outs.

ai asic automation cad gdpr +7 skills
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