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Intern - Digital IP Design Engineer, DRAM
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Senior engineer building and improving ASIC verification infrastructure, CI/CD flows, and AI-assisted debug tools for GPU development at NVIDIA.
Digital Design
Designs and verifies semiconductor logic for communication chips using Verilog/SystemVerilog, CDC tools, and emulation platforms to ensure zero-defect silicon.
Principal Staff Silicon Design Engineer - DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for AMD server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware requirements.
Lead Design Verification Engineer
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Junior Digital Design Engineer
Designs and verifies digital integrated circuits for IoT and automotive using VHDL/Verilog, with a focus on signal processing and low-level embedded software.
Digital Design Engineer
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows for complex SoCs to improve test coverage and silicon yield.
Senior Digital Design Engineer
Design and lead digital architectures for power-management ICs in automotive and industrial systems using Verilog/SystemVerilog, verification flows, and EDA tools.
Senior Manager/Deputy Director, ASIC Digital Design IP Engineering
Lead a team to design and deliver next-gen processor and SoC IP, driving RTL development, verification, and silicon execution while optimizing power, performance, and area.
ASIC Digital Design IP Engineer
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL, and PPA trade-offs with cross-functional teams.
Digital Design Engineer
Designs and verifies digital RTL subsystems for semiconductor products, using SystemVerilog/Verilog and collaborating with architecture and verification teams.
Design Verification Engineer
Design Verification Engineer at AMD builds and runs SystemVerilog/UVM testbenches to validate DDR5, LPDDR5, and DFI memory interfaces for server products, collaborating with hardware, firmware, and software teams.
Design Verification Engineer
Design Verification Engineer at AMD responsible for verifying DDR interfaces (DDR5, LPDDR5/LPDDR6) and memory protocols (DFI) using SystemVerilog, UVM, and C/C++ in server products.
Design Verification Engineer – Physical AI Compute
You develop and execute verification strategies for complex SoC components and systems. You build SystemVerilog and UVM verification environments, define coverage goals, verify hardware and software interactions,…
Senior Electrical / Hardware Engineer
Design FPGA-based replacements for obsolete avionics hardware and lead DMSMS mitigation while ensuring DO-254/DO-160 compliance for safety-critical defense systems.
Staff Design Verification Engineer
Design Verification Engineer at Cerebras building and validating the world's largest AI chip, ensuring first-silicon success through SystemVerilog/UVM testbenches and cross-functional collaboration.
Mixed Signal Design Verification Engineer
Designs and verifies mixed-signal ICs, building simulation environments and automated regressions to ensure silicon meets specs before tapeout and aligns with customer needs.
2027 Internship - FPGA Engineer
Intern designs FPGA/ASIC hardware for ultra-low-latency trading systems, writing RTL in SystemVerilog, verifying with vendor tools, and deploying to live silicon.