2027 Internship - FPGA Engineer
Summary
Intern designs FPGA/ASIC hardware for ultra-low-latency trading systems, writing RTL in SystemVerilog, verifying with vendor tools, and deploying to live silicon.
Virtu is a leading financial firm that leverages cutting edge technology to deliver liquidity to the global markets and innovative, transparent trading solutions to our clients. As a market maker, Virtu provides deep liquidity that helps to create more efficient markets around the world. Our market structure expertise, broad diversification, and execution technology enables us to provide competitive bids and offers in over 19,000 securities, at over 235 venues, in 36 countries worldwide.
Virtu's internship programme offers students an extraordinary opportunity to learn about the firm and the world’s financial markets. We have built a thoughtful and challenging curriculum with projects that introduce students to the many complex and ever-changing problems to solve. Students can expect a company-curated global training week for our interns, real trading and quantitative problems to solve throughout the programme, and engaging social events to get to know our team and culture.
- Location: Dublin, Ireland (onsite)
- Dates: 10 week programme, starting 21 June 2027 - 27 August 2027
- Training: Ongoing training throughout the summer
- Projects: Real problems to solve throughout the programme. Interns will work from a list of projects and have several senior mentors throughout the programme.
- Perks: Daily catered lunches, fully stocked kitchen, on-site gym & workout classes, games room, social events and laundry service.
THE ROLE
At Virtu, our internship is designed to put you at the very center of ultra-low latency trading. You will tackle the actual engineering challenges that keep our trading systems competitive, paired with experienced engineers who mentor you through projects where every nanosecond counts.
Our hardware team designs both FPGA and ASIC solutions that sit at the heart of our market-making infrastructure. You'll work across the full design lifecycle — from architecture and RTL implementation through simulation, verification, and bring-up on live hardware. At the end of your internship, you'll have turned an idea into something real, tangible, and running on silicon. No finance background is required. We are looking for curious engineers who thrive on hard problems at the boundary of hardware and software. What matters most is how you think and how you learn.
Requirements
- Academic background in Electrical or Computer Engineering
- Experienced with Hardware Description Languages (SystemVerilog, Verilog)
- Experience working with FPGA vendor tools — Vivado or Quartus for FPGAs
- Comfortable with Software programming languages (Python, C++, or similar)
- Interested in learning how FPGAs and ASICs are used in the context of low latency trading systems
- Strong problem solving and communication skills
- Graduating year of 2028
Virtu Financial is an equal opportunity employer, committed to a diverse and inclusive workplace, welcoming you for who you are and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status.