AccelerComm

NewBe an early applicant HybridUK

12 hours ago

Design Engineer

You will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile…

NewBe an early applicant HybridSenior

12 hours ago

Senior Design Engineer

We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This…

NewBe an early applicant HybridUKSenior

14 hours ago

Senior Design Engineer (0093)

Agile AI C++ FPGA Python +4 skills

You will work on revolutionary technology that is at the leading edge of satellite communications, a 5G base station to be deployed on board satellite. This technology will underpin the next generation of mobile…

7 days ago

Graduate Design Engineer

New HybridUK

AI Asic Bash C++ Ethernet +12 skills

AccelerComm attracts people who want to work on the cutting edge 5G/6G satellite communications that are powering global connectivity - technology that is genuinely advanced and problems that are genuinely hard. Our…

last month

Software Engineer

Open 40d HybridUK

Bash C++ Embedded Systems FPGA Groovy +3 skills

Develops and optimizes low-level C/C++ code for 5G NR physical layer systems, focusing on real-time performance on embedded platforms with SIMD, multi-threading, and hardware acceleration (FPGA/DSP).

Open 50d HybridUKPrincipal

Principal Design Team Leader

Agile AI C++ FPGA Pre-sales +5 skills

Leads a hardware design team developing 5G baseband IP for satellite-based base stations, focusing on power efficiency and delivery of Layer 1 IP using RTL, FPGA, and ASIC techniques.

Open 50d HybridNorth AmericaSenior

Senior Hardware Design Engineers

United States

Designs and implements FPGA/ASIC hardware for satellite-based 5G base stations, focusing on signal processing and power efficiency using Verilog/SystemVerilog and EDA tools.

Open 50d HybridNorth America

Design Engineers

United States

Design Engineer at AccelerComm develops advanced IP, system, and board solutions for 5G wireless communications, using SystemVerilog, EDA tools, and hardware optimization techniques.

Automation Confluence C++ Git Jenkins +6 skills

Senior Design Engineer

Open 62d HybridUKSenior

Designs RTL implementations (Verilog/SystemVerilog) for ASIC and FPGA, working on cutting-edge 5G satellite base station technology for non-terrestrial communications. Core technologies include digital design, FPGA/ASIC development, signal processing, and EDA tools.