AccelerComm
Open positions
Senior System Architect
A Senior System Architect at AccelerComm defines communications product and IP architectures for 5G physical-layer processing, translating system and customer requirements into designs across software, FPGA and ASIC. Day to day this means requirements capture, architectural modelling and trade-off analysis (performance, resources, power) alongside algorithm, FPGA and ASIC engineers, plus customer
Principal System Architect
A senior technical leadership role in AccelerComm's Systems Engineering team: the Principal System Architect defines product architectures for 5G communications IP, leads FPGA/ASIC trade-offs and requirements analysis, guides customer/partner technical engagements, and mentors engineers. Core focus: 3GPP 5G NR physical layer, signal processing, modem design, and FPGA-to-ASIC implementation.
Design Team Leader
Hands-on team leadership role at AccelerComm in Cambridge (hybrid) guiding the design, quality, and delivery of Layer 1 IP for 5G base stations on satellites. The leader drives RTL design for ASIC/FPGA, UVM verification, timing/power optimisation, and mentors the team while shaping the technical roadmap.
Design Engineer
You will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile…
Project Manager
Project Manager at AccelerComm (Southampton, hybrid) who plans, tracks and reports on customer and internal IP development projects for wireless and satellite communications. Day to day involves scheduling, risk/RAID management, budget tracking and stakeholder reporting using Microsoft Project and JIRA with a blend of agile and waterfall.
Senior Design Engineer
We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This…
Software Engineer
Develops and optimizes low-level C/C++ code for 5G NR physical layer systems, focusing on real-time performance on embedded platforms with SIMD, multi-threading, and hardware acceleration (FPGA/DSP).
Senior Hardware Design Engineers
Designs and implements FPGA/ASIC hardware for satellite-based 5G base stations, focusing on signal processing and power efficiency using Verilog/SystemVerilog and EDA tools.
Senior Design Engineer
Designs RTL implementations (Verilog/SystemVerilog) for ASIC and FPGA, working on cutting-edge 5G satellite base station technology for non-terrestrial communications. Core technologies include digital design, FPGA/ASIC development, signal processing, and EDA tools.