AccelerComm
Open positions
Design Team Leader
Hands-on team leadership role at AccelerComm in Cambridge (hybrid) guiding the design, quality, and delivery of Layer 1 IP for 5G base stations on satellites. The leader drives RTL design for ASIC/FPGA, UVM verification, timing/power optimisation, and mentors the team while shaping the technical roadmap.
Design Engineer
You will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile…
Senior Design Engineer
We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This…
Senior Hardware Design Engineers
Designs and implements FPGA/ASIC hardware for satellite-based 5G base stations, focusing on signal processing and power efficiency using Verilog/SystemVerilog and EDA tools.
Design Engineers
Design Engineer at AccelerComm develops advanced IP, system, and board solutions for 5G wireless communications, using SystemVerilog, EDA tools, and hardware optimization techniques.
Senior Design Engineer
Designs RTL implementations (Verilog/SystemVerilog) for ASIC and FPGA, working on cutting-edge 5G satellite base station technology for non-terrestrial communications. Core technologies include digital design, FPGA/ASIC development, signal processing, and EDA tools.