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Advanced Micro Devices, Inc

American multinational semiconductor company

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158 jobs

CPU Core Physical Design Engineer

Open 90d 2 weeks ago98 viewsSenior
United Kingdom
Cambridge

Lead the physical design team to create next-gen CPU cores, balancing power, performance, and area while collaborating with cross-functional engineering groups.

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Staff Silicon Design Engineer

2 weeks ago28 viewsStaff
Ireland
Dublin

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

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RTL Design Engineer - PCIE, Ethernet, USB and DDR

2 weeks ago5 views
India
Bangalore-Technostar B1

RTL design engineer at AMD's Bangalore site who develops and integrates in-house/vendor IPs, subsystems, and SoC designs with a focus on PCIE, Ethernet, USB, and DDR. Day to day involves running static quality checks (LINT, CDC, RDC, CLP/VCLP), owning SDC/UPF constraints, and driving timing closure and verification with stakeholders.

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Lead FPGA Timing & Characterization Silicon Design Engineer

2 weeks ago67 viewsLead
India
Hyderabad-Sattva

At AMD in Hyderabad, lead the development, validation, silicon correlation, and release of FPGA timing models — driving characterization methodology, automation, and QoR analysis to power FPGA implementation and timing analysis tools like Vivado. Requires 10+ years in FPGA timing/STA and an MTech/MS in Electronics.

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Silicon Design Engineer

2 weeks ago7 views
Taiwan
Hsinchu

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

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Sr Physical Design Engineer

Open 16d 2 weeks ago26 viewsSenior
United States
CA, Santa Clara

Senior physical design engineer at AMD working on high-performance multi-gigabit SerDes PHY and advanced IP blocks. Day to day: drive RTL-to-GDS implementation — synthesis, floorplanning, timing-driven place & route, clock tree synthesis, and signoff — while optimizing timing, power, and area and improving automated design flows.

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RTL Design Engineer

Open 59d 3 weeks ago74 views
India
Hyderabad-Sattva

Design verification engineer on AMD's Verification Engineering team in Hyderabad, developing and maintaining functional/performance tests, testbench components, and hardware emulation environments for next-generation processor IP. Core technologies: C/C++, SystemVerilog, UVM, and emulation tooling.

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Silicon Design Engineer

Open 16d 3 weeks ago11 views
Singapore

RTL digital design engineer on AMD's FPGA Product Development Silicon Integration team in Singapore: integrates IP from multiple design teams into next-generation FPGA/SoC products, builds and verifies full-chip RTL connectivity models, and develops custom tooling — using Verilog/SystemVerilog, ASIC CAD tools (VCS, Design Compiler, Primetime), and Python/Perl/Shell scripting.

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Staff Silicon Design Engineer – Physical Design

Open 16d 3 weeks ago14 viewsStaff
Singapore

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

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Lead PD/ Physical design Engineer

Open 18d 3 weeks ago56 viewsLead
India
Hyderabad-Sattva

Lead engineer at AMD's Hyderabad site who plans, implements, and verifies physical design for processor subsystem IPs, driving block- and top-level implementation through tapeout signoff. Core work spans 5nm-and-below nodes, low-power processor designs, and EDA tools like Innovus, Fusion Compiler, and PrimeTime with Perl/shell scripting.

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RTL Design Engineer

Open 18d 3 weeks ago37 viewsSenior
ON, Markham-1CV

RTL IP design engineer on AMD's Security IP (SECIP) team, doing block-level RTL design and subsystem integration of embedded microprocessor subsystems and hardware accelerators (security, crypto, compression, DMA, power management) across AMD SoCs. Core stack: Verilog/SystemVerilog, ASIC design flows, AXI/AMBA protocols, Python/Tcl scripting.

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CPU Core RTL Design Engineer

Open 18d 3 weeks ago35 views
United States
TX, Austin

Designs and implements RTL for next-generation high-performance CPU cores on AMD's central core RTL team, contributing pipeline logic and microarchitecture features across client, server, and AI platforms. Core technologies: Verilog/SystemVerilog, CPU microarchitecture, synthesis, timing closure, and pre/post-silicon debug.

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ASIC Design Engineer, PCIe IP Enablement

Open 18d 3 weeks ago36 views
ON, Markham-1CV

Design and integrate AMD's PCI Express (PCIe) subsystem IP into SoCs: RTL implementation, synthesis with timing/lint/CDC closure, test/debug/clock design, and UPF-based low-power flows, working across IP, physical design, and SoC teams. Core stack: Verilog/RTL, synthesis/CDC/LEC/STA tools, UPF power-aware design.

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Lead Physical Design Engineer

Open 35d 3 weeks ago57 viewsLead
India
Bangalore-Technostar B3

Senior silicon design engineer at AMD in Bangalore focused on electromigration and IR-drop (EMIR) analysis, debug, and signoff closure for complex high-performance SoC designs using Ansys RedHawk-SC and Cadence Voltus. Works with physical design, power, and package teams to root-cause power integrity issues and improve EMIR methodology and automation.

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Lead Silicon Design Engineer

Open 19d 3 weeks ago62 viewsLead
India
Hyderabad-Sattva

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SENIOR STAFF SILICON DESIGN ENGINEER

Open 17d 3 weeks ago16 viewsStaff
Ireland
Cork

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

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Sr. Staff Physical Design Engineer

Open 20d 3 weeks ago33 viewsStaff
BC, Vancouver

Senior physical design engineer at AMD owning complex multi-million-gate graphics IP blocks for next-gen AI data center chips. Day to day: floorplanning, synthesis, place-and-route, clock tree synthesis, timing closure, extraction, and physical verification/signoff on advanced nodes, plus flow automation (Python/TCL), methodology, and mentoring, based in Vancouver, BC or Markham, ON.

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Silicon Design Engineer

Open 20d 3 weeks ago12 views
China
Shanghai-B49

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

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Silicon Design Engineer (1 year contract)

Open 20d 3 weeks ago23 viewsContract
ON, Markham-1CV

A 1-year contract at AMD's Central DFX group in Markham, ON, implementing Design-for-Test/Design-for-Debug features in complex APU, game console, and GPU ASICs. Day to day you build automated design flows, write Perl/Python/TCL tooling, monitor CAD/IP regressions, and develop in-house automation and AI/ML applications.

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RTL Design Engineer

Open 117d 3 weeks ago43 views
India
Hyderabad-Sattva

RTL Design Engineer at AMD working on SOC integration for IO peripheral subsystems (UFS, SDIO, Octal SPI) targeting ARM/RISC-V processor systems. Requires 4-5 years of RTL design experience, expertise in protocols like AXI, processor, interconnect, and microarchitecture design for semiconductor products.

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