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RD-數位前端設計工程師 ASIC Digital Design Engineer (Front-End)
HybridAPAC
Taiwan
Zhubei City, Hsinchu County【Key Responsibilities / 工作內容】 1. Micro-Architecture & RTL Design：Define system/module specifications, micro-architecture, and write clean, synthesizable Verilog / SystemVerilog RTL code for high-performance SoCs. 2.…
Automation Firmware FPGA PCIe Perl +6 skills