RD-數位前端設計工程師 ASIC Digital Design Engineer (Front-End)

【Key Responsibilities / 工作內容】
1. Micro-Architecture & RTL Design：Define system/module specifications, micro-architecture, and write clean, synthesizable Verilog / SystemVerilog RTL code for high-performance SoCs.
2. Post-RTL Design Flow Integration：Execute front-end post-RTL design flows including Logic Synthesis, Linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks.
3. Verification & Debugging：Work closely with DV (Design Verification) engineers to develop test plans, resolve functional bugs, and cover assertion-based verification.
4. Timing & Power Optimization：Define SDC constraints, run Static Timing Analysis (STA) at early stages, and implement low-power design techniques (UPF/CPF).
5. Silicon Bring-up：Support post-silicon validation, FPGA prototyping, and work with firmware/software teams for system integration.

【Requirements & Qualifications / 條件要求】

• Education：Master’s degree in EE, CS, or Microelectronics.
• Technical Skills：

1.Deep knowledge in Verilog / SystemVerilog.
2.Hands-on experience with front-end EDA tools (e.g., Synopsys Design Compiler, SpyGlass, VCS, Verdi).
3.Familiar with high-speed interface protocols (e.g., PCIe, USB, AXI/AHB bus structures).
4.Scripting skills in Python, Tcl, or Perl for workflow automation.