아이디어스투실리콘
Open positions
Design Verification Engineer/대구
주요업무 We are seeking a skilled Design Verification Engineer with 5+ years of experience and strong expertise in UVM (Universal Verification Methodology) to lead verification efforts for complex SoC/IP blocks. The…
Digital Logic 개발/분당R&D
주요업무 ㆍSoc 개발 ㆍDigital IP 개발 ㆍVerilog RTL coding and simulation ㆍLogic Synthesis/STA ㆍSystem Verilog/UVM을 이용한 Verification ㆍFunctional Safety Logic Insertion ㆍDFT 자격요건 ㆍ경력 3~15년 우대사항 - 복지 및 혜택 유연 근무제 운영 / 자율 복장제 시행 중식비…
Digital Logic 개발/대구
주요업무 ㆍSoc 개발 ㆍDigital IP 개발 ㆍVerilog RTL coding and simulation ㆍLogic Synthesis/STA ㆍSystem Verilog/UVM을 이용한 Verification ㆍFunctional Safety Logic Insertion ㆍDFT 자격요건 ㆍ경력 3~15년 우대사항 - 복지 및 혜택 유연 근무제 운영 / 자율 복장제 시행 중식비…
Design Verification Engineer/분당R&D
주요업무 We are seeking a skilled Design Verification Engineer with 5+ years of experience and strong expertise in UVM (Universal Verification Methodology) to lead verification efforts for complex SoC/IP blocks. The…