AMD
American multinational semiconductor company
Open positions
Lead Hardware Systems Design Engineer
Leads architecture, design, validation, and debug of cloud-scale server platforms and complex PCBs in AMD's Data Center Platform Engineering Group — from schematics and layout through bring-up and production. Core work spans high-speed hardware design (PCIe, DDR, Ethernet, USB, SAS/SATA), signal/power integrity, and cross-team technical leadership.
RTL Methodology Silicon Design Engineer
Builds and owns the RTL design methodology, tooling, and AI-powered capabilities for AMD's next-generation CPU core in Austin, TX. Day to day: maintaining linting/static-analysis flows and HDL parsers/AST tooling, and developing LLM-based assistants and agentic workflows to accelerate RTL design, review, and debug.
Silicon Design Engineer
1-year contract at AMD's Central DFX group in Markham: implement and deploy automated Design-for-Test (DFT) flows for complex SOC ASICs (APU, game console, GPU products), run design checks, debug CAD/IP regressions, and build automation with Perl, Python, and TCL, including in-house CAD utilities and AI/ML apps.
Silicon Design Engineer
Senior silicon design engineer on AMD's Fullchip Floorplan CAD team in Shanghai, owning full-chip physical design methodologies and CAD automation for large-scale SoC designs — from concept through production deployment — using Tcl, Python, and Perl with tools like Cadence Innovus and Synopsys Fusion Compiler/ICC2.
Senior Staff Physical Design Engineer
Own end-to-end physical design of multi-million-gate AMD graphics IP blocks for next-gen AI data center chips — floorplanning, synthesis, CTS, routing, timing closure and signoff on advanced nodes, using tools like Synopsys ICC2/Fusion Compiler, Cadence Innovus, and Mentor Calibre, with Python/TCL flow automation and mentoring. On-site in Vancouver, BC or Markham, ON.
Senior Staff Silicon Design Engineer
An SMTS-level analog circuit design engineer on AMD's Ireland SerDes team, designing and verifying high-speed analog circuits (ADC/DAC, equalizers, clocking, drivers) for 200+Gbps SerDes on advanced CMOS FinFET nodes, supporting connectivity for AMD CPU, GPU, and FPGA products.
Staff Silicon Design Engineer
AMD is hiring a Staff Silicon Design Engineer in Belgrade to define and execute hardware emulation test plans: building emulation testbenches, debugging with design and verification teams, and bringing up standard interfaces. Core technologies include SystemVerilog/Verilog, UVM, C/C++, FPGA flows, and AMBA/PCIe/CXL protocols.
ASIC Design Engineer, PCIe IP Enablement
At AMD in Markham, ON, this engineer integrates and implements AMD's PCIe subsystem IP into SoCs, owning digital IP from architecture through tape-out. Day-to-day work spans RTL design, synthesis, timing/lint/CDC closure, UPF-based low-power flows, and scripting for flow automation.
CPU Core RTL Design Engineer
Design and optimize RTL for next-generation high-performance CPU cores in AMD's central core RTL team, working on pipeline logic and microarchitecture across client, server, and AI platforms. Core tech: Verilog/SystemVerilog, out-of-order CPU design, timing/power optimization, synthesis, and Python/Tcl scripting.
RTL Design Engineer
Designs block-level RTL and integrates embedded microprocessor subsystems and hardware accelerators (security, cryptography, compression, DMA, power management) on AMD's Security IP team, supporting client, server, graphics, and gaming SoCs. Daily work centers on Verilog/SystemVerilog design, debugging regressions, and ASIC signoff flows.
Staff Silicon Design Engineer, Physical Design
Staff engineer on AMD's Singapore silicon design team owning PnR, STA and physical design integration from design handoff through timing convergence, verification and signoff. Work combines EDA tools (Fusion Compiler, Innovus, PrimeTime, Calibre) with Tcl/Python/Perl automation and AI-assisted, agentic workflows.
Silicon Design Engineer
Silicon Design Engineer on AMD's FPGA Product Development Silicon Integration team in Singapore, integrating RTL components into next-generation FPGA and programmable SoC products — building full-chip RTL connectivity models, verifying them against architectural intent, and developing internal tooling. Core stack: Verilog/SystemVerilog, SoC/ASIC design flows, and CAD tools like VCS, Verdi, and Pri