Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Design high-performance Ethernet MAC engines and network datapaths for AI-driven ASICs, ensuring line-rate performance and protocol compliance using SystemVerilog and AI-assisted flows.
Design and implement memory controllers, hierarchies, and near-memory accelerators for AI-driven ASICs, optimizing bandwidth, latency, and power for ML workloads using SystemVerilog and AI-assisted flows.
Design and own the on-chip interconnect fabric and high-speed I/O subsystems for AI-driven ASICs, implementing AMBA-compliant NoC routers, crossbars, and bridges to ensure low-latency, high-bandwidth data movement in production silicon.
Leads hardware verification for AI-generated chip designs, ensuring rigorous validation of custom ASICs at tapeout stage using SystemVerilog, UVM, and Python, while collaborating with AI/ML and architecture teams to refine verification strategies and methodologies.
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new…
About Architect Architect is an AI lab for the compute stack, starting with chip design. We build AI systems to design on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML…
About Architect Architect is an AI research and product lab for chip design. We build AI models and systems that can explore, design, optimize, and verify new hardware. Our goal is to reimagine chip design using AI,…
We couldn't check your fit for this role — add a CV to your profile to see it next time.