AUREXIS TECH PTE. LTD.
3 jobs
2 weeks ago
Senior/ IC Design Engineer (Physical Design)
APACSenior
Singapore
Designs and implements ASIC physical design flows (RTL-to-GDS) using AI-assisted EDA tools, focusing on synthesis, timing closure, and tape-out verification.
ai automation bash cpp llm +5 skills
2 weeks ago
Senior/ IC Design Engineer (Physical Design)
APACSenior
Singapore
Designs and implements ASIC physical design flows (RTL-to-GDS) using EDA tools and AI-assisted methodologies to optimize PPA and timing for tape-out.
ai automation bash cpp llm +5 skills
3 weeks ago
Senior/ IC Design Engineer (Design Verification)
Open 22d APACSenior
Singapore
Design verification engineer building and running SystemVerilog/UVM testbenches to validate ASIC/SoC designs, using AI-assisted tools to improve coverage and debug efficiency.
ai automation generative-ai machine-learning perl +3 skills
60 000 – 120 000 SGD