Ethernova
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Senior ASIC (Front-End) Design Engineer
Open 139d North AmericaSenior
United States
Senior ASIC front-end design engineer at Ethernovia owning all aspects of digital SoC design — micro-architecture, RTL, verification, synthesis, CDC, LEC and STA — for advanced automotive Ethernet networking chips. Hybrid role in San Jose, working with architecture, software and verification teams to take high-performance custom silicon from spec to silicon.
AI C++ Ethernet Networking PCIe +7 skills
200K – 300K $ 10 views 2 months ago
Senior ASIC Design Verification Engineer
Open 139d North AmericaSenior
United States
Senior ASIC Design Verification Engineer at Ethernovia (San Jose, CA) owns end-to-end digital SoC verification of automotive Ethernet networking semiconductors, planning and executing verification with architects, designers and SW engineers. Core stack: SystemVerilog, UVM, Python, TCL, C/C++.
AI Asic Automation C++ Ethernet +9 skills
200K – 300K $