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Builds and optimizes an agent system framework for AI-driven automation, integrating LLM-based reasoning, tool execution, and orchestration in a production environment.
FuriosaAI is seeking a Software Engineer to develop AI reference applications and maintain internal services to support their AI-native compute platform. The role involves building RAG and agentic systems, creating sample code, and collaborating with the global developer community.
Build and refine AI-assisted engineering workflows for FuriosaAI’s compiler team, optimizing development, debugging, and CI using LLM tools and automation to boost team productivity.
FuriosaAI is seeking a Software Engineer to develop the front-end of their AI compiler, focusing on model ingestion, graph-level optimizations, and the design of a tensor-level kernel language. The role involves translating deep learning models into internal representations and collaborating on compiler infrastructure to maximize performance on AI hardware.
FuriosaAI is seeking a Software Engineer to develop middle-end compiler optimizations for their AI inference hardware. The role involves designing IR abstractions, scheduling algorithms, and performance models to improve the efficiency of deep learning workloads on specialized compute platforms.
FuriosaAI is seeking a Software Engineer to design and implement high-performance kernels for their proprietary AI-native compute platform. The role involves optimizing AI model performance on hardware, developing diagnostic tools, and enabling end-to-end programming for AI workloads.
Design PyTorch-native kernel integration layers and runtime environments to execute custom AI kernels efficiently within PyTorch, optimizing for hardware control and tensor programmability.
Develops firmware/software for NPU management interfaces, handling communication between host systems and AI accelerators via protocols like MCTP/PLDM, while ensuring telemetry, health monitoring, and compliance with industry specs.
Develop and maintain Linux PCIe device drivers and kernel modules for FuriosaAI's AI-native compute platform, optimizing DMA, IOMMU, and high-performance I/O pipelines.
Develops firmware/software for NPU management interfaces, handling communication between host systems and AI accelerators. Focuses on power, performance, and thermal telemetry, protocol compliance (MCTP/PLDM), and system-level validation for AI hardware.
Develops and maintains low-level firmware for AI-native SoCs, including ROM code, bootloaders, and secure boot, while collaborating with hardware teams on SoC bring-up and validation.
Leads AI hardware system PCB design, including schematic capture, layout, and SI/PI consulting for FuriosaAI’s AI-native compute platform.
Leads silicon validation for NPU SoC chips, ensuring system-level functionality from first silicon bring-up to performance optimization and stability. Bridges hardware (RTL/DV) and software (firmware/OS) teams with structured validation processes, debugging, and test automation.
Develops autonomous agent systems that solve complex engineering problems via AI-driven exploration, optimization, and self-improvement, integrating LLM post-training and multi-agent workflows for production-grade solutions.
Builds and maintains AI-native compute infrastructure for FuriosaAI’s NPU-based systems, focusing on reliability, observability, and automation to ensure scalable, secure, and efficient production services.
Mechanical engineer at AI chip maker FuriosaAI who designs and develops the mechanical structure of AI accelerator NPU cards, servers, and rack systems using PTC Creo — handling 3D modeling, tolerance/interference reviews, prototyping through EVT/DVT/PVT, and design-for-manufacturing (CNC, sheet metal, die casting, injection molding) alongside cross-functional teams.
About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…
Software engineer on FuriosaAI's MLSys team enabling frontier LLMs on the company's NPU chips: analyzing model architectures, writing and optimizing Tensor Contraction Language (TCL) kernels (attention, MoE), integrating models into the Furiosa-LLM inference stack, and validating correctness and performance. Core stack: Python, PyTorch, TCL DSL, with Rust/C++ code reading and vLLM/SGLang technique
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