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About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…
AI Research Engineer developing proprietary LLMs for agentic tasks, RL post-training pipelines, and frontier AI research at a Korean AI chip company, primarily using PyTorch and deep learning frameworks.
As an AI Research Engineer Intern at FuriosaAI, you will conduct research on advanced AI models, focusing on areas like LLMs and RL, and contribute to the development of a proprietary AI compute platform. You will work with PyTorch and other deep learning tools to build high-performance AI solutions.
You'll prototype next-generation LLM serving concepts (attention-FFN disaggregation, KV cache reuse/compression) directly on FuriosaAI's NPU hardware, proving them via POCs with the company's kernel programming stack and feeding insights back into research. Core tech: LLM inference internals, vLLM/SGLang/TensorRT-LLM, CUDA/Triton accelerator programming.
Designs AI-native hardware architectures and RTL implementations for high-performance, energy-efficient AI chips, focusing on chip modules, simulation, and optimization for power, timing, and area.
Hardware Design Verification Engineer at FuriosaAI responsible for defining and implementing verification plans, building test benches, and debugging design failures using SystemVerilog/UVM methodologies and EDA tools.
Designs and optimizes AI hardware architectures, focusing on performance, power, and area (PPA) metrics. Uses Verilog, EDA tools, and scripting to perform synthesis, equivalence checking, and timing analysis for chip-level designs.
Designs and executes verification strategies for AI hardware, ensuring functional correctness and coverage of block/system-level designs using SystemVerilog/UVM and Python-based tools.
Designs AI-native SoC architectures and RTL for high-performance, energy-efficient AI compute hardware, collaborating with verification, physical implementation, and silicon bring-up teams to ensure optimal performance and manufacturability.
Design and optimize signal/power integrity for AI hardware, running EM/circuit/system simulations and guiding chiplet/3D-IC layouts to ensure robust AI-native compute.
Validates NPU SoC hardware for FuriosaAI, ensuring first-silicon bring-up, system-level debugging, and performance optimization across AI compute components like NPU cores, CPUs, and high-speed interfaces.
Designs end-to-end thermal solutions for AI hardware (NPU/ASIC to server chassis), balancing cooling methods (air/liquid/immersion) via CFD simulations and real-world testing to optimize performance and reliability.
Designs and implements enterprise-wide security infrastructure under Zero Trust principles, including policy, access control, cloud security, and incident response for an AI hardware startup.
Build and optimize a high-performance inference engine for LLMs and multimodal models on FuriosaAI’s NPUs, collaborating with compiler and hardware teams to maximize throughput and efficiency.
FuriosaAI is seeking a Senior Software Engineer to design and implement the low-level runtime stack for their NPU hardware. The role involves developing firmware, optimizing asynchronous execution pipelines, and enabling multi-node inference using Rust, C, or C++.
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