FuriosaAI

last month

Production Engineer, LLM Serving

Open 35d APAC

AI Automation Cloud C++ Distributed Systems +17 skills

About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…

last month

Software Engineer, LLM Performance & Evaluation

Open 35d APAC

Acceptance Criteria AI Automation C++ Data Pipelines +13 skills

About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…

last month

Software Engineer, Build Systems & Release Infrastructure

Open 35d APAC

AI Automation Bash Bazel CentOS +12 skills

About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…

Software Engineer, Site Reliability Engineer

Open 65d APAC

AI API Automation Cloud Cloud Native +6 skills

Builds and maintains AI-native compute infrastructure for FuriosaAI’s NPU-based systems, focusing on reliability, observability, and automation to ensure scalable, secure, and efficient production services.

Hardware - Silicon Validation Team Lead (NPU SoC)

Open 65d APACLead

AI Automation Bash CI/CD C++ +10 skills

Leads silicon validation for NPU SoC chips, ensuring system-level functionality from first silicon bring-up to performance optimization and stability. Bridges hardware (RTL/DV) and software (firmware/OS) teams with structured validation processes, debugging, and test automation.

Hardware - Silicon Validation Engineer (NPU SoC)

Open 65d APAC

AI Automation Bash CI/CD C++ +10 skills

Validates NPU SoC hardware for FuriosaAI, ensuring first-silicon bring-up, system-level debugging, and performance optimization across AI compute components like NPU cores, CPUs, and high-speed interfaces.

Hardware - Senior SoC Design Engineer

Open 65d APACSenior

Designs AI-native SoC architectures and RTL for high-performance, energy-efficient AI compute hardware, collaborating with verification, physical implementation, and silicon bring-up teams to ensure optimal performance and manufacturability.

AI Automation FPGA Rtl

Hardware - Senior Design Verification Engineer

Open 65d APACSenior

AI Automation Bash Ethernet PCIe +4 skills

Designs and executes verification strategies for AI hardware, ensuring functional correctness and coverage of block/system-level designs using SystemVerilog/UVM and Python-based tools.