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About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea…
Hardware Design Verification Engineer at FuriosaAI responsible for defining and implementing verification plans, building test benches, and debugging design failures using SystemVerilog/UVM methodologies and EDA tools.
Designs and executes verification strategies for AI hardware, ensuring functional correctness and coverage of block/system-level designs using SystemVerilog/UVM and Python-based tools.
Validates NPU SoC hardware for FuriosaAI, ensuring first-silicon bring-up, system-level debugging, and performance optimization across AI compute components like NPU cores, CPUs, and high-speed interfaces.
Builds and optimizes an agent system framework for AI-driven automation, integrating LLM-based reasoning, tool execution, and orchestration in a production environment.
FuriosaAI is seeking a Software Engineer to develop the front-end of their AI compiler, focusing on model ingestion, graph-level optimizations, and the design of a tensor-level kernel language. The role involves translating deep learning models into internal representations and collaborating on compiler infrastructure to maximize performance on AI hardware.
Leads silicon validation for NPU SoC chips, ensuring system-level functionality from first silicon bring-up to performance optimization and stability. Bridges hardware (RTL/DV) and software (firmware/OS) teams with structured validation processes, debugging, and test automation.
Builds and maintains AI-native compute infrastructure for FuriosaAI’s NPU-based systems, focusing on reliability, observability, and automation to ensure scalable, secure, and efficient production services.
Design and deploy AI/LLM models on FuriosaAI’s RNGD NPU using the Furiosa SDK, running POCs, benchmarks, and debugging for US customers while translating technical capabilities into business value.
Software engineer on FuriosaAI's MLSys team enabling frontier LLMs on the company's NPU chips: analyzing model architectures, writing and optimizing Tensor Contraction Language (TCL) kernels (attention, MoE), integrating models into the Furiosa-LLM inference stack, and validating correctness and performance. Core stack: Python, PyTorch, TCL DSL, with Rust/C++ code reading and vLLM/SGLang technique
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