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HPR is the leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1…
Develop and debug high-performance C applications for ultra-low latency electronic trading infrastructure on multi-core Linux systems, collaborating with tier-1 financial institution customers.
Develops high-performance, low-latency trading infrastructure in C for financial institutions, focusing on multi-core Linux systems and network data processing.
Designs and optimizes ultra-low-latency FPGA hardware for electronic trading systems used by top-tier financial institutions.
Designs, tests, and maintains high-performance FPGA/ASIC systems for ultra-low-latency trading infrastructure, using SystemVerilog for verification and advanced simulation tools.
Maintains and secures the company’s low-latency trading infrastructure, handling Linux/Windows servers, endpoints, patching, SIEM, and data-center hardware in a regulated financial environment.
FPGA Design Engineer responsible for RTL design, development, and optimization of high-performance, ultra-low latency FPGA compute and networking systems for electronic trading infrastructure, primarily using SystemVerilog/VHDL.
Supports and troubleshoots ultra-low latency trading infrastructure for top financial firms, using Linux, Python, and networking expertise.
Build FPGA-based ultra-low-latency trading systems in Verilog/VHDL, automate RTL generation, and collaborate on real-time capital-markets infrastructure.
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