HPR (Hyannis Port Research)
Open positions
Senior FPGA Design Engineer
Designs and optimizes ultra-low-latency FPGA hardware for electronic trading systems used by top-tier financial institutions.
Senior Design Verification Engineer
Designs, tests, and maintains high-performance FPGA/ASIC systems for ultra-low-latency trading infrastructure, using SystemVerilog for verification and advanced simulation tools.
FPGA Design Engineer II
FPGA Design Engineer responsible for RTL design, development, and optimization of high-performance, ultra-low latency FPGA compute and networking systems for electronic trading infrastructure, primarily using SystemVerilog/VHDL.
FPGA Engineering Intern - Summer 2027
Build FPGA-based ultra-low-latency trading systems in Verilog/VHDL, automate RTL generation, and collaborate on real-time capital-markets infrastructure.
