巨有科技股份有限公司
Open positions
APR Physical Design Engineer
1.Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2.Responsible…
Mixed-Mode IC Design Engineer
Familiar with CMOS design concept,SPICE simulation,IC LAYOUT technique,and debugging skill.Experience in ADC/DAC,OP,PLL,MEMORY design is a plus
FPGA TO ASIC Design Engineer
Front-End RTL Coding & Verification (I/O peripherals and MCU) Altera&Xilinx FPGA Application development C-Coding
SOC/ASIC Design manager
熟VLSI 設計,HDL coding. 熟Design USB,IEEE1394,MPEG,DISPLAY,DSP,uP.為佳
資深SOC/ASIC Design Engineer
熟VLSI 設計,HDL coding. 熟Design USB,IEEE1394,MPEG,DISPLAY,DSP,uP.為佳
IC佈局工程師
1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible…