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資深數位IC設計工程師/Senior SoC Design Engineer
New APACSenior
Taiwan
Zhongshan District, Taipei CitySenior digital IC / SoC design engineer in Taipei: does RTL coding and digital circuit design, integrates and develops mass-production chips with full tape-out experience, builds SoC verification flows (functional verification, DFT: Scan/MBIST/Boundary Scan), and integrates systems over AXI, AHB, APB, PCIe, and DDR.
PCIe Rtl