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資深數位IC設計工程師/Senior SoC Design Engineer
New APACSenior
Taiwan
Zhongshan District, Taipei CitySenior digital IC / SoC design engineer in Taipei: does RTL coding and digital circuit design, integrates and develops mass-production chips with full tape-out experience, builds SoC verification flows (functional verification, DFT: Scan/MBIST/Boundary Scan), and integrates systems over AXI, AHB, APB, PCIe, and DDR.
PCIe Rtl
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開發工程師/數位IC設計工程師
APAC
Taiwan
Zhongshan District, Taipei City1.負責 數位電路設計與 RTL Coding，進行晶片功能開發與整合。 2.參與 高速介面 (SerDes) IP 開發，包含設計、驗證與效能優化。 3.訊號處理與通訊演算法硬體化，將演算法轉換為可實作的 RTL 架構並進行效能調校。 4.與跨部門團隊合作，完成 SoC 整合、驗證及量產流程。
Rtl SerDes