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Senior SoC FPGA Digital Design and Verification Engineer
HybridAPACSenior
Taiwan
Zhubei City, Hsinchu CountyThe Role: High-Speed RTL and SoC Integration You will be responsible for RTL design, SoC integration, and high-speed timing closure of key digital blocks within the Xilinx Versal ACAP. This role sits at the…
Firmware MATLAB Rtl Simulink SystemVerilog +2 skills