Senior SoC FPGA Digital Design and Verification Engineer

The Role: High-Speed RTL and SoC Integration
You will be responsible for RTL design, SoC integration, and high-speed timing closure of key digital blocks within the Xilinx Versal ACAP. This role sits at the intersection of hardware and software, requiring deep expertise in digital design best practices, advanced verification methodologies, and a functional understanding of Model-Based Design for DSP implementation.

Key Responsibilities

RTL Design and Implementation
-Develop and implement robust, high-performance RTL (Register Transfer Level) using Verilog or SystemVerilog for key functional blocks within the Versal ACAP.
-Focus on blocks related to high-speed data path, clocking, control, and interaction with the RF front-end.

SoC Integration and Bus Interfacing
-Integrate complex IP blocks and custom logic within the SoC structure, managing data flow across the Versal’s Application Processor Fabric and Programmable Logic.
-Implement and configure AMBA AXI protocols (AXI4-Lite, AXI4-Stream, and AXI4-Full) for efficient system-level communication and data transfer.

Verification and Testing
-Employ advanced verification techniques, including developing testbenches and components within the Universal Verification Methodology (UVM) framework.
-Define and implement verification flows that cover hardware/software co-verification, leveraging UVM-SW to test firmware access to custom hardware registers and logic.

High-Speed Constraints and Timing Closure
-Define and achieve timing closure for high-frequency digital logic used within the 26 GHz RF system architecture.
-Analyze and resolve complex timing violations, managing clock domain crossings (CDC) and synchronous logic paths to meet stringent performance targets.

Algorithm Implementation and Register Maps
-Implement DSP algorithms—often derived from MATLAB/Simulink models and auto-generated code—into optimized RTL structures.
-Design, document, and maintain Register Maps that serve as the interface between custom hardware and embedded firmware running on ARM processors within the Versal ACAP.

Collaboration
-Work closely with Firmware Engineers, RF Engineers, and SoC Architects to ensure RTL, firmware, and analog interfaces align with system requirements.